EMI Solutions for Six-Layer PCB Stackups: A PCB Designer's Guide

[@skelly62]

Great video Zach. No doubt it will help a lot of newer designers.

[@ksathara]

Kudos Zach and Altium Academy for this great piece. I would also like you touch base with instances you cannot avoid splits on high edge-rate signals. I use small caps near the split and the signals. Also about how good is edge ground region to prevent leaking at the edge.

[@abdurrahmanbaylan4099]

Is it possible to perform SI & PI simulations by Altium? How did you analyze the board in terms of SI/PI?

[@gunay-turan]

In the initial stackup with SIG on L3 and L4, the two ground planes are sharing the return currents with the same coupling on the layers above and below. In this case, how do we handle the crosstalk between L1 - L3 and L4 - L6 signals? Can orthogonal routing be used as a general solution to avoid crosstalk issues? And as always, thanks for the great video! @Zachariah-Peterson

[@husseinaljawazri5322]

Hi Zach Can you explain why impedance discontinuity and mismatch creates radiation and EMI problems

[@petersage5157]

Nicely explained. 6-layer is beyond the needs of anything I'd build, but this is interesting. tl;dw: Close coupling between the signal layers and ground; thicker core to reduce coupling between the internal signal layers. That solid power region in the hand-on example is essentially a shielding can. V0, V+, don't really make no nevermind - they're both ground as far as the signal is concerned. In fact, with faster edge rate signals, it can be beneficial to have coupling between both the V0 and V+ rails.

[@jimjjewett]

Starting around 10:20, you discuss routing over splits in the power plane -- but I would expect coupling to the nearby ground plane to be 40-50 times stronger, so that power plane discontinuities couldn't approach the 5%-10% tolerance of controlled impedance. Are these signals particularly sensitive? Is the tolerance for controlled impedance _variation_ within a single board much tighter than the overall target? At 11:48, when routing over splits in the power plane -- does serpentining within the split affect the timing skew? Is that typically modeled by the tools, or just something to watch out for and manually request a field-solving simulation there?

[@jebinsatheeshkumar]

GND pouring on signal layer, will help to reduce the Radiation? If yes can you pls explain how its helping.

[@rfrisbee1]

I'd put the PWR layer closest to the layer where the high speed components and their decoupling capacitors are mounted to minimise the loop inductance. ETA: I.e. if components on L1, GND on L2 and PWR on L3.

[@thomassorensen7907]

When L3(Power) is used as a reference plane for L4(signal), even though the distance is "large", wont there be some field spreading as the field has to rely on decoupling capacitors as return path?

[@BlackNSB]

Zack, Would there be issues with having power layer 3 and signal on layer 4 in terms of coupling? I realize that you have ground on layer 5 for layer 4 to couple to, but I'm trying to parse what Rick Hartley is recommending vs. what you have here. He's basically saying to have: SIG/PWR GND SIG/PWR GND SIG/PWR GND

[@cedricb2344]

Hi, does having a reference layer close to the power plane make a big difference for decoupling ? With a 6 layer stackup as shown with one or two power plane layers in comparison with an basic 4 layer sig-gnd-pwr-sig stackup.

[@jimjjewett]

Was this stackup (8:45) an in-progress draft, or were there some subtle choices that would be worth explaining? It looks like the thick center layer is "Dielectric", the ones near it are "core" and the outer ones are "prepreg". Is "dialectric" just a way to say the fabricator can choose? (It does list a specific Dk, different from either the core or prepreg, but that might be a default.) Is it common to use so many different materials? Is this for cost-savings, and more relevant at volume? The L3-Power layer is only half-ounce copper, even though all the other layers -- including its symmetric L4 -- are full-ounce. In the past, when I've seen an asymmetry, it was to _increase_ the thickness of a power plane. Was this a copper-balance concern, or something I haven't even considered?

[@williameyvaz5565]

I assume those internal layer 4 routing of the DDR signals referencing to that power plane (L3) have the same potential.

[@jimjjewett]

At 9:13 and 9:17, the vias seem to be labelled. Is that just a nice feature of the Altium User Interface, or is that silkscreen on tented vias? If it will show on the actual board, what made the vias more annotation-worthy than other pads?

[@stephenjbro]

Those are through-hole pads, and Altium (along with other ECAD software) will display the net names in the GUI. These aren't in silkscreen layers or anything like that.

[@AlbertRei3424]

I assume that the cutout on the inner layer around the ddr traces was used necessary to achieve the target impedance. I would increase the cutout area to have the external traces (the one on top and the one on the bottom) not influenced by the pour.

[@Zachariah-Peterson]

Good eye, after filming we put the board through fabrication and we did provide some larger margin to that polygon cutout border.

[@thomassorensen7907]

@@Zachariah-Peterson I assume we are talking about the cutout 10:28 on layer 4. How are the cutout influencing the traces on the top and bottom layer?

[@burakkahraman5438]

@AlbertRei3424 I did not understand how the area of the cutout region on the internal layer that is away from external layers (especially from top layer) affects the signals on external layers

[@Zachariah-Peterson]

@@burakkahraman5438 He is referring to the traces near the edge of the cutout, not external layers

[@ostrov11]

Привет, Зак.

[@behnammadadnia3410]

Nice