FIR filter using IP with Vivado

[@w8ryanb]

Many thanks going through your process... exactly what I was looking for!

[@vahidMeghdadi]

Happy to hear that :)

[@wafaelhajhmida3863]

Hi professor, I have just discovered your KZbin channel ! keep doing great work👏. Wafa your phd student

[@vahidMeghdadi]

many thanks Wafa !!

[@热血愤青]

Hi! If I want to display the magnitude response by Vivado, I want to know what I should do?

[@tempusFugit1337]

Hi, if i understand right you put a generated sine-wave in at JA-Pin and from there to XADC and from there into your FIR-Filter and from there to the output pin JB. But how you generate an analog signal from the output-bit-values of JB-Pin ? (Because filtered input Signal of Analog Discovery seems to be a sine wave too). Does Analog Discovery have a kind of DAC at input ? Greetings

[@vahidMeghdadi]

Hi, yes in fact the JB signal is an 8-bit digital output. I used a simple 8-bit passive DAC from digilent (Pmod R2R: Resistor Ladder DAC).

[@msaideroglu]

Thanks for video. I guess you are using Analog Discovery tool of Digilent. Can I see your demo setup details? I need to do it also for an fir filter design.

[@IlliaAZARKH]

I'll try to apply it to my testing code in LabVeiw, actually I have a proble with the output of the FIR, but I think the problem is a clock. Great video.

[@Ankitsingh-my1vu]

Hi did you solve your problem?

[@IlliaAZARKH]

@@Ankitsingh-my1vu yes, the problem was in the parameters of the clock. Since 4 month I'm using it for my projet and it works great.

[@Kianam2]

Incredible explanation 😊

[@chankinw]

Thanks for the explanations. It would be great if the amplitude of your voice was multiplied by 2. Could you please also run a demo on the IIR implementation?

[@vahidMeghdadi]

Sorry about the voice. I will think about IIR, however the IIR filters are a little hard to implement in fixed-point with FPGA.

[@ninaelizabethfarroaguilar6828]

Hi, how do you configured the waveforms? I can't understand how to implement the vhdl code in waveforms to see the simulation. I hope you can answer me.

[@vahidMeghdadi]

The waveforms is a driver for Discovery2 (from digilent see: digilent.com/shop/analog-discovery-2-100ms-s-usb-oscilloscope-logic-analyzer-and-variable-power-supply/). Actually it is not a simulation, but a simple real signal generator and an oscilloscope.

[@annankldun4040]

This video is awesome. Thank you!

[@MonishaK-sh9bk]

is there any simulation code for testing?

[@brajkishorrajput9238]

please sir share programing in 3-tap FIR Filter comman used programming in used vivado software

[@mohammedalshehri1593]

Why did you make the input x as(16 bits) and the output is 8 bit? Why they arn't same?

[@vahidMeghdadi]

Because had a simple 8-bit CNA :) However, I used 16 bits to improve the precision in the intermediate calculations.

[@Bustoutfunk]

At 3:15 you took the max value from Num and also multiplied Num by 512. What was the purpose of this? Why not just copy those original Num values into Vivado?

[@vahidMeghdadi]

I needed the coeff on 7 bit. That's why I scale all the coef to have integers in the range [-63,63]. The range [-38,38] was selected arbitrary and you may scale by another factor.

[@m1geo]

@@vahidMeghdadi I, too, am confused here. Could you elaborate? Where is the requirement for 7 bit?

[@vahidMeghdadi]

@@m1geo Actually there is no requirement, you should fix anyway the number of bits to something. In the normal applications (not too high quality) 5 to 7 bits are sufficient to represent the coefficients. All you must make sure, is that there is no overflow when you represent your data. I took 7 bits. So the coefficient dynamic can go from -64 to +63. Maybe, instead of scaling by 512, it is better to multiply all the coef by (value)/(max_value)*63 to have 7 bits.

[@m1geo]

@@vahidMeghdadi Very interesting! I have a been copy/pasting the scaled -1 to 1 values. The output is super distorted. I cannot work it out. The input signal is good, but the output is just distorted noise.

[@annankldun4040]

@@vahidMeghdadi why did you use 512 though? That is 2^9.

[@miladdalim1]

very useful thanks for the content

[@gauravpurohit1234]

do we require any special license to use the Waveforms

[@vahidMeghdadi]

No, waveform is free and downloadable from digilent, but you need the "discovery board" from digilent also.

[@gauravpurohit1234]

@@vahidMeghdadi I am a little confused, Ok let me explain, You are taking two analog inputs ->via analog board->it goes to your experimental FPGA Board (how) -> how you are showing output waveforms. Please help me in this flow. The question is How does input go to FPGA (XADC) and come out to Waveforms?

[@gauravpurohit1234]

Sorry * via Discovery Board

[@vahidMeghdadi]

@@gauravpurohit1234 The analog output of discovery board is connected to the XADC of the Basys board, through JA(4) and JA(0) wires. The 8-bit digital output signal is connected to Digilent PMOD R2R, a simple DAC, through JB. You can take a look into www.unilim.fr/pages_perso/vahid/XADCinBasys3.html where more details can be found.

[@gauravpurohit1234]

Many thanks Dr. Vahid. I am grateful for your urgent actions and help.

[@bakeronews1]

I miss speaking French 😢. Thanks for the tutorial though.

[@vahidMeghdadi]

:))

[@firashammad5775]

Audio is bad,content is good but very hard to hear without an external speaker.

[@anishchandran3653]

Regret to say that the audio is too feeble to understand

[@mubasheer5584]

It would be good if you had explained bit by bit so that the new learner like me would understand it better 🙄.

[@brajkishorrajput9238]

plz sir share your any contact details

[@Ankitsingh-my1vu]

From where you got sampling frequency as 100khz

[@vahidMeghdadi]

Hi Ankit, In the main prog, I have a process that divide the 100 MHz clk by 1000 to generate a 100 kHz signal, which is applied to convst.

[@Ankitsingh-my1vu]

@@vahidMeghdadi in my FPGA i have XADC which has sampling rate of 1MSPS than should i assign the sampling frequency of my FIR filter as 1MHZ ?or should fs be the internal clock of my FPGA in my case ?

[@Ankitsingh-my1vu]

@@vahidMeghdadi also i have one more question , what if my data is coming at every clock rising edge and not on xadc alone so what to assign to _s_axis_data_tvalid ?

[@vahidMeghdadi]

@@Ankitsingh-my1vu As I understand from your question, in the FIR filter design, you should put the real sampling frequency, which is for you 1 MSPS. It is because the designer needs the ratio between clk frequency and sampling frequency to optimize the filter taps.

[@vahidMeghdadi]

@@Ankitsingh-my1vu I think that it cannot work because the IP needs several clk cycles to compute the output, but I am not sure !

[@MonishaK-sh9bk]

Is there any simulation code for testing?

[@vahidMeghdadi]

No, sorry, I have not the simulation.