FPGA Course - The Basics #01

This is the first video about our FPGA introduction course, on this video we're going to learn the basics about FPGA, and create 2 simple labs using Vivado.
All the labs on this video were using the Zeboard.
Source code: goo.gl/BjFgf7
The complete course playlist can be found here:
• FPGA Course - The Basi...
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[@abahadoran]

Finally, some content that actually makes me progress learning about FPGAs! Thank you so much for dedicating time and energy to creating these outstanding videos!

[@Stabby666]

This is a great intro course, dude. Thanks for the hard work :)

[@TheDevelopmentChannel]

Thanks for watching.

[@ipan6587]

I think even the little baby agrees its a good tutorial

[@TheDevelopmentChannel]

hahaha

[@kedarpednekar7896]

thanks brother , FPGA kits are costly so one may not be able to buy them ,but such tutorials will help students a lot. keep it up

[@naveenchoudhary2675]

thank you so much brother... GOD bless YOu.. :)

[@rajeshkumbhakar271]

Appreciate you handwork man..

[@yinsencai8995]

I learned a lot from your course. Thanks a lot!

[@tareknagla3141]

EXCELLENT

[@joerit633]

Great tutorial!! Thank you!!!

[@ricarenado]

Fabuloso vídeo amigo. Parabéns!

[@ghobadkhorsand4879]

Great video

[@user-xb5zu6zu7j]

Thank you sir

[@jangarsenerken6270]

my English is quite weak. but I'm really interested in FPGA

[@Aemilindore]

Have you heard of tiny FPGA? If we buy it can we continue with tutorial series?

[@raheelaliali4846]

I followed all the steps mentioned in the above video but i was unable to generate the bit stream it gives me the following errors: 1) [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: A[0], B[0], C[0], D[0]. 2) [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. kindly let me know where i have made a mistake .Thanks for this help full video.

[@thewhitefalcon8539]

Go to the implementation view, go to the I/O Ports window (or if it's not visible then select in the menu Window -> I/O Ports) and make sure every input/output you used has a pin selected. Otherwise it doesn't know which pin is supposed to be which signal.

[@EdwardYamunaque]

why are you prefer Verilog ?? and VHDL?

[@TheDevelopmentChannel]

EDWARD JOSE Hi Edward, actually you need to learn both, sometimes on day job, you can choose, sometimes not, on this tutorial I've started with Verilog just because it's similarities with C, also Verilog is less typed than VHDL, but VHDL gives more support to large projects. To resume really you need to know both, and when I finish the Vivado HLS course I will also teach Matlab HDL coder, and then switch back to VHDL.

[@THEREALDATALORD]

@@TheDevelopmentChannel If you program in Xilinx Pynq it converts to verilog or vhdl.

[@karastom2304]

Hi can you please recommend book we can use it, and also what is the perquisite I have to know before I learn FPGA

[@TheDevelopmentChannel]

+Takey Asaad Hi, look normally I use these books at work: (Advanced Chip Design, Practical examples with Verilog, and Circuit Design with VHDL)

[@karastom2304]

Hi are you going to cover more if not do you know other website teach FPGA(video course) .

[@TheDevelopmentChannel]

+Takey Asaad Hi again, Yes I'm going to cover more with FPGA design, right now I'm working on the part 2 of the image processing with FPGA (using Vivado HLS), also I'm working on course of using STM32F4 microcontrollers with mbed as well) Regarding other free courses about FPGA I like a lot these: kzbin.info/www/bejne/r4W4poOnf6l8hJY But if you are interested on a payed one here: www.doulos.com/knowhow/fpga/ Do you have some topic to cover in mind? Anyway thanks for the feedback I will try my best to cover everything related to embedded design (Including FPGA, microcontrollers, control engineer, image processing)

[@benitoa6238]

For your truth table you omitted don't care x and high impedance Z for your gates