FPGA Implementation of Verilog Code|Quartus|Part23

[@zindaginamilegidobara3372]

Sir...your lectures are really informative and interesting.... Kindly upload all the lectures in this lecture series.

[@AmirFarjam-z2i]

Awesome, Thank you

[@ranjeetkumar2709]

will u show xilinx fpga board implementation using virtex

[@boppanaramaseshu7717]

Hi Sir good explanation, I am facing issues with reconfigurable pll, simulation, i am using quartus lite version 17, 18 [ free intel altera modelsim] i am not able to do pll ip core simulation verilog ip core . I am getting error loading design while simulating ip in modelsim can you please do the video with step by step explanation of intel altera pll & reconfigurable pll ip core with .mif streaming simulation. please do the needful waiting for your new video...Thank you