Pipelining - Question 5

[@rohitrai6261]

how can we start decoding the sub instruction in the third cycle we don't have the value of R4 at that point in time.

[@abhijeetchauhan4111]

I guess, when not mentioned we have to consider forwarding from e to d as well as e to e, unlike the q.6 video where it is mentioned that fwding only from e to d.

[@vaishudharan2402]

Decode (D), and Instruction Execution (E) and Write Operand (W) stages. The F, D, and W stages take one clock cycle each for any instruction. The E stage takes one clock cycle for ADD and SUB instructions, three clock cycles for MUL instruction, and six clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. (i) What is the number of clock cycles needed to execute the following sequence of instructions? (ii) Justify your answer with neat diagram. Instruction Meaning of instruction I0:MUL R0,R1, R2 R2= R0 *R1 I1: DIV R3,R4, R5 R5 = R3/R4 I2:ADD R5,R2, R2 R2 = R5+R2 I3:SUB R2,R6, R5 R5= R2-R6

[@jayeshdewangan5896]

Gate 2009 question -28 please sir there is a confusion please solve it asap...

[@DeepakKumar-pm7ie]

Unlock your all video pls