Thank you this helped me provide a example of this program for my senior project!
@ramamurthyj57035 жыл бұрын
great work sir please continue
@TeamVLSI5 жыл бұрын
Thanks Rama :)
@StayInBliss6 жыл бұрын
Thanks sir, learnt a lot...
@TeamVLSI5 жыл бұрын
Thanks Anish
@parimalarenga925 жыл бұрын
What is the system requirement to run this cadence software?
@TeamVLSI5 жыл бұрын
Hi Parimala, Minimum requirement is very lesser, But a machine having 2GB RAM, 500GB HDD, 64bit Linux and i3 processor and higher configuration is fine for general use.
@parimalarenga925 жыл бұрын
What about graphics card can i run this with Integrated graphics card or i need dedicated graphics card?
@TeamVLSI5 жыл бұрын
Integrated graphics is also fine.
@donvu53284 жыл бұрын
What options do you have turned on for the XStream In? I streamed in a GDS file that has hierarchy; but the layout cell had all of its hierarchy flattened and only holds the polygon. I want the XSream In to keep all the same hierarchy as the GDS file.
@TeamVLSI4 жыл бұрын
Hi Don, Yes, Hierarchy will be maintained. Please quote the time line of video so I can answer you specifically.
@donvu53284 жыл бұрын
@@TeamVLSI At the 2:05 mark in the video (after you've specified the GDS file, library, and techlib), your mouse is just above the "Show Options" but you didn't click through it. I'd like to compare your options settings to compare against mine since it's yielding flat polygons. Thanks!
@mohammedafzal5345 жыл бұрын
Can you tell me what is the difference between full custom & semi custom design
@TeamVLSI5 жыл бұрын
Hi Mohammed Basically in full custom design, We start design with scratch, where as in semi custom design, we use some pre designed and characterized IPs, macros or cells instead of developing everything from scratch.
@mohammedafzal5345 жыл бұрын
Thank you sir, but in cadence we mostly call every cell from tech library right, then those are all called semi custom or what we called them?
@pavankori69864 жыл бұрын
can you provide a video in cadence how to generate lef file
@TeamVLSI4 жыл бұрын
Hi Pavan You could run the following command in innovus intractive terminal to dump the .lef file. >set lefDefOutVersion 5.8 >write_lef_abstract -PGPinLayers M7 -stripePin -specifyTopLayer M7 filename.lef # In the above command set LEF version and metal layers as per your design.
@mohammedafzal5344 жыл бұрын
Can i know how to convert layout into gds file?
@TeamVLSI4 жыл бұрын
Hi Afzal, You can use "streamOut" command in Innovus along with its required switches.
@alamurisanjeev51265 жыл бұрын
Waht is exact difference between def file and GDSII file
@TeamVLSI4 жыл бұрын
There is no basis of comparison, both contains different information.
@tuongluongthanh20305 жыл бұрын
thanks
@durgeshaddala55744 жыл бұрын
Can I get free pdk files? If it impossible explain me how to add pdk files to cadence.
@TeamVLSI4 жыл бұрын
Hi Durgesh, Although there is no general way of adding a PDK but you can refer this video: kzbin.info/www/bejne/qIvUhGaGpdGlY68