Generic Array Logic Hand Disassembly of the JEDEC File (Part 1 of 2)

[@rpocc]

I love your accent combined with the subject of the video. And by the way, the explaination was super-simple for a complete noob in PLAs like me. Thanks, dude!

[@mondocommodore]

Top!! Grande spiegazione, ottimo tutorial

[@DRI1966]

Only one word : Respect ... I learned a lot THANK YOU :)

[@laserquant]

That was a lot of fun 😀👍

[@saadnaseem891]

Great job

[@NivagSwerdna]

The first two lines made a lot of sense... but why the zeroes in the third and subsequent lines didn't contribute has left me confused.

[@PeepawMcDonald]

Yes you are correct. It does seem a bit confusing. But imagine we have an eight input "AND Gate" And we are only using two inputs. We must do something with the other six unused inputs. So we activate the unused inputs so that they are automatically activated. So two of the inputs to the "AND Gate" are derived from Input pins to the GAL. But the other six inputs to the "AND Gate" are always tied active high and enabled. So they can in effect be ignored. I hope I didn't muddy the waters again with my explanation. The nice thing is that when you create the JEDEC code for the GAL. The software you use to make the code takes care of this process automatically. Thank you so very much for a great question :)

[@2TAK322]

The Bob Ross of JEDEC files

[@lovepreetsinghgill517]

The viewing quality of this video is poor, but video contentvise is so good

[@표대인]

hi~ wonderful job~ can you help me,,to do disassembly for altera ep310 jedec fille