Gigabit Ethernet Hardware Design - Phil's Lab

[@youriklaassens7198]

Never clicked faster on a Phil's Lab video than this one. Just wanted to say that I genuinely appreciate your quality of videos that you continuously push out.

[@PhilsLab]

Thank you very much!

[@rallymax2]

10000%

[@EmbeddedEnigma]

man never clicked so fast on the video in my life. I am recently designing Gigabit PoE PSE and was looking for some references and was even going to look at your previous ethernet video and here you uploaded the exact thing. Love you

[@PhilsLab]

That's awesome, thank you - hope all goes well with your design!

[@abobakeralhadar8854]

Ethernet is such a complex topic but when you came to this you make the Most professional and simplified content as usual i think i will make my own one after this video really appreciate your work keep going with much complex ones ❤

[@PhilsLab]

Thank you very much for your kind comment!

[@mikeselectricstuff]

Something that can be useful to know is that it's not necessary to length-match between pairs from the Phy to the magjack - I was unsure of this when doing an unusal GbE application, so did some testing and found that it was quite happy with an extra metre of cat5 on one pair!

[@PhilsLab]

Yep, exactly! I put that as a note in the video as well in the PCB MagJack section. Super interesting though that even having a length-difference of 1m still worked!

[@cedricb2344]

I think your PHY performed some kind of wizardry there aha. It is true that length matching diff pairs is absolutely not needed if the pairs are routed symmetrically. (Not possible with some THT connectors) Even better with good uniform prepreg. The tight requirements on pair is generally to allow the system to work in spite of a bad link like in general a bad cable.

[@jefflongo]

Recently had to teach myself all this stuff for work. I would have killed for this video a couple months ago! Excellent video with the perfect amount of depth.

[@PhilsLab]

Thank you very much, Jeff!

[@Jonathan-ru9zl]

I'm an embedded engineer but your videos are always worth watching ✔☺

[@timschulz9563]

Thanks for the video! I'd love to see a video about PoE in the future.

[@siralee4911]

I'm planning on implementing some POE smarthome devices and this is actually very useful (as always)

[@PhilsLab]

Awesome, good luck with your designs!

[@nathannation]

It would be the most epic thing if you did a piece or two on PoE specifically PSE and PD.

[@M_Gargantua]

Would love a follow on device that can do PoE or USB or External, and the resulting mess of smart power switches to prevent backfeeding or overvolting anything during hotswaping.

[@bubbasplants189]

Thanks Phil! You're a legend for sharing all these videos for free! I've applied some of the knowledge to projects to learn more and it's helped get my resume noticed a lot easier. Keep up the great work!

[@PhilsLab]

Great to hear that these videos have been helpful for your projects, thank you!

[@AzaB2C]

Neat! Thank you for this one Phil. Love your content, even if my brain is resistant to fully acknowledging and understanding at the data rate you're imparting knowledge.

[@PhilsLab]

Haha thank you very much!

[@MaX271]

Very good quality video as per usual! Pretty exhaustive end-to-end instructions 👍 However there is some 'gotcha' that's not necessarily well know about RGMII. in the base spec, data are emitted synchronous with the clock, which means that the setup time requirement for the reception part isn't met. Either you have to add ~1ns of delay on the clock with a lengthened trace, either the PHY (or maybe MAC) have a retiming functionality built-in. Even though it seems like most PHY integrate this functionality, it's still something to be verified when choosing a matching PHY-MAC combination

[@PhilsLab]

Thank you, and yes, very good points I should've mentioned! The PHYs in many cases seem to integrate this functionality (flexible adjustment of RGMII delay, either via strapping or MDIO), from what I've seen across multiple devices.

[@miskoL0L]

This is what I needed right now! Perfect timing!

[@PhilsLab]

Awesome, glad to hear that!

[@almc8445]

Bruh I was just doing some research into this very topic a month or so ago - I couldn’t find any good information, so this is perfect!

[@hristiyanvasilev1720]

This is an excellent video and channel. Thank you for the content and the quality of the videos. Very valuable content.

[@PhilsLab]

Thank you for your kind words!

[@asprillamangombe8560]

Awesome video .Its always a pleasure to learn form you .

[@PhilsLab]

Thank you!

[@brannonmcevers1854]

Phil, another great video! Thanks for sharing your experience and insights. I have an idea for a video. I know you're into audio electronics (as am I). Could you do a video regarding correct PCB design for an audio power amplifier (discrete class AB). These boards are constrained to only 2 layers, they have high and low Z signal sections. Large rectified half sines can be induced into the small signal. Top it all off with a NFB loop that connects input to output. I think a video like this would be valuable for any high power PCB design. Thanks again!

[@kiprof4350]

Hi Phil!, thank you so much for making such a video. This kind of information is truly extremely valuable. Maybe, similar to the Advanced Hardware Design course you did previously, you could provide a course about the design of this nice PCB as well? 😉

[@PhilsLab]

Thanks a lot for watching! Still working on a new course, which will most likely be an extension ('advanced') to the mixed-signal hardware course!

[@kiprof4350]

@@PhilsLab It's really nice to hear that Phil! I had noticed that the above beautiful PCB is for your new course, I'm eagerly awaiting your new course.This will really be a great! Thank you very much!

[@PhilsLab]

@@kiprof4350 Many thanks again! :)

[@EngineerAnandu]

Thank u Sir.

[@fedimakni1200]

Thank you for the amazing videos and all the details. Could you make a video about the issues we may face when connecting 2 PCBs with long wires? (power and signal issues - filtering - inductance - how to choose the wires ... and how to solve most of the issues) thanks again.

[@PedrinCBr]

Hi Phil, how are you? My name is Pedro and I'm studying engineering here in Brazil, my final course project is an aeropendulum and your control system design videos have helped a lot, do you have the continuations of this series? I only found the first 3

[@patrickrostami]

Perfect video as usual 👌

[@PhilsLab]

Thank you, Patrick!

[@Neywiny]

I would've liked to have seen some mention of current-mode vs voltage-mode PHYs and how you have to choose the magnetics correctly. I couldn't find in the RTL8211 datasheet what the drive mode is, but a lot of dev boards copy-paste old MDI designs with newer PHYs and get it wrong.

[@Bajran_]

Wow this is awesome !!! too high level for me.

[@natsudragneel293]

Can you do a video on esp32-s2 UAC, along with the firmware and testing?

[@konturgestalter]

FINALLY! amazing

[@PhilsLab]

Thank you!

[@SkyLab_Aerospace_LTD]

Hi Phil, did you release the schematics for your M.2 FPGA Video?

[@norm1124]

thanks for the great video

[@gustavwahl]

Always enjoy your videos!! Just wodnering have you ever considered doing a tutorial video series from design to a fully finished product? (Similar to your Kicad hardware design tutorials, but going one step further with a specific use case)

[@PhilsLab]

Thanks, Gustav! I'd like to make a tutorial series like that, but unfortunately it seems that KZbin + extended tutorial videos (split across multiple videos) don't give terribly many views.

[@gustavwahl]

@@PhilsLab Ohh that's unfortunate, would definetly to see any short showcase of a finished product you have made

[@sanjikaneki6226]

Will you also do a vid on the Petalinux+ linux driver part of the bring up?

[@C.AMohammedMeeran]

Hello Phil, I am a mechanical engineering student. I am interested in learning PCB designing because I am currently working on a mechatronic project that uses microcontrollers, sensors, and some analog and digital circuits. Can you suggest a learning path for how I should start my PCB designing journey from basic to advanced? Can you suggest some PCB designing resources?

[@a.villegas3414]

Amazing!!! A long run video! Thank you for all the knowledge that you share with us

[@PhilsLab]

Many thanks for watching!

[@akshatmodi4843]

Hey super nice video buddy! Absolutely fantastic work... Could you also make a video on how to setup a STM32 F4 / F7 chips with LAN 8742A ethernet controllers? The standard STM Schematics are really difficult to work with 😅 But keep going with the great content, Respect ❤

[@kanyethegoatnocap]

i just finished my first ever pcb thanks to you, i would love if you could give me a small fast review if possible, it would help me prevent losing money and time also thanks a lot for making all these videos accessible for everyone , much love from africa

[@PhilsLab]

Congrats on finishing your first PCB! I'd suggest posting your design in the PCB sub-reddit for a review.

[@andrewlloydwebber2616]

Great video!

[@PhilsLab]

Thank you!

[@learner7040]

Hello, I am using KiCAD and would like to start learning high speed PCB Design. Could you please suggest your videos or other resources for the same? Thank you!

[@aneeshprasobhan]

I designed one in the past few months and to be honest, I spent too much time researching about the Bob Smith termination xD

[@liliansirbu840]

Thank you so much. A few months ago I had to dig in all this because of RGMII and RMII, where I used same ICs. We have a similar approach to such design. BTW, if the traces are longer than 2inches, make sense to add a clock buffer IC, or buffers on each line? Other question migh be from another topic. Are you controlling Phy registers over MDIO interface, or leave them by default, or let Phy do by its own the negotiation with a lan hub? I am ot sure if you have mentioned that, but the difference between RGMII and RMII on the same clock speed, is that the first one is sampling data because of DDR pins properties of FPGA or ASICs. This is important if the design is not related to the PS (SoC) where all this is arranged already. I used in my design the generic FPGA banks.

[@PhilsLab]

I've never needed to add buffers to these lines, but then again I haven't run the RGMII signals longer than that before. Regarding PHY registers, yes, these I am controlling via MDIO.

[@liliansirbu840]

@@PhilsLab thank you for quick response. Do you have a video where you are handling MDIO registers? BTW, in case if someone want to analyse the MDIO, the pulse-view can decode that data.

[@pranjalkushwaha197]

Hi Phil, it was a very informative video with awesome explanations. I had a small question. In the latest altium academy video where Zach Peterson compares CircuitMinds's auto-generated schematic with a human one at 8:35 he says that diode protection is a nice add to protect against SD card insertion/removal ESD events. Is this a concern for RJ-45 as well?

[@PhilsLab]

Thank you! The topic of ESD protection for Ethernet deserves a video on its own. But in short: yes, all/most external interfaces should have adequate ESD protection tailored to requirements of that system. For Ethernet we have the 'issues' of isolation (separate GNDs possible, often can only use TVS diodes differentially, etc.), but also inherent ESD protection in the magnetics/PHY. For simple, home-use boards like this, for Ethernet I haven't found the need to add additional ESD protection devices. For more detail, check out: m.littelfuse.com/~/media/electronics/application_notes/esd/littelfuse_ethernet_electrical_threats_and_protection_application_note.pdf.pdf&ved=2ahUKEwjisKXLj42IAxUl0wIHHVs4Onw4ChAWegQIChAB&usg=AOvVaw36fmFoTe5xXUS4iqTgiS_x There are also a number of examples on the Electronics StackExchange that go into more detail.

[@pranjalkushwaha197]

@@PhilsLab Hi Phil, thanks for answering and linking the resource.

[@milindjani7118]

Awesome video and great content. What do you usually do for VCC pin on RJ45 connector? As I see in the datasheet, it is center-tap to the transformer!

[@PhilsLab]

Thanks! Depends on the PHY/system set-up. Some PHYs are 'current-mode'/open-collector drivers and require a voltage attached to the center-tap. Alternatively, other use cases are PoE, for example. For these types PHY, such as in the video, I generally leave it floating.

[@awocrf]

Do you make these PCBs for yourself or for work? Are these available somewhere as a finished product?

[@PhilsLab]

The PCBs shown in the YT vids are all personal ones. I'm afraid they aren't currently for sale.

[@ameenibrahim7519]

Phils can you help me in building electronic circuit, i need only the power circuit , the circuit is for psd laser sensor. If you can please let me know. Thank you.

[@politismos3929]

I've been looking for a video like this.... Downloaded saved. Oooooo I'm boutta make a name for myself here

[@Chris-hi2hn]

Does anyone have an example implementing the zynqs ethernet controller. Particularly the remote pc interfacing it, I have a similar setup and building a udp interface using vitis.

[@bobby9568]

Github link doesn't contain this schematic...😅

[@MrKerim2000]

Was kostet eigentlich das ganze Projekt?

[@PhilsLab]

Das hat für die Prototypen (2 Stück) ca. 1450 USD inkl. Leiterplatten + Bestückung + Komponenten gekostet.

[@chengL10]

Is there a new online course coming soon ?

[@PhilsLab]

Still working on one - possibly next year!

[@jeffbeasley8235]

great video. always an easy click for me when I see you have uploaded. one comment -- the audio cuts in this particular video really annoyed me. it felt in many cases that one sentence was barely finished when the next one came in on top of it, especially in the first half of the video (and even sometimes, mid-sentence an edit was obvious and jarring). I know that editing is very time consuming and you're probably doing it yourself, but that is my honest feedback and I hope it's constructive.

[@PhilsLab]

Thanks for the feedback, Jeff. I'll listen back to the video and try to improve for future videos. Edit: Just had a scan through the video to listen, but can't quite pick up on what you mean (probably just used to how I edit these!) - could you please provide some example timestamps where this happens? Thanks!

[@sopheaktrachhorn3401]

What is the via size for impedance control trace?

[@PhilsLab]

For these 'not-too-high-speed' designs, via sizing isn't too important. As the overall via length can be considered a lumped element and only presents a very short impedance discontinuity. I use vias that I'm already placing in my design (e.g. 0.7mm pad, 0.3mm drill) and if I'm spaced-constrained will reduce drill and pad sizes.

[@timeltdme4355]

i am curious about this ascope