Hardware Software CoDesign with Vivado and Vitis

[@SciHeartJourney]

Thank you! Vitis doesn't seem so scary to me anymore.

[@iyyappanr957]

Very good tutorial.. Can you tell me which debugger are you using for programming and debugging in this video? Which one is good to use for multiple CPU's and FPGA core debugging?

[@rijojohn5062]

Hi Sir, Kindly do a video tutorial on using DPUs and its profiling.....

[@boppanaramaseshu7717]

Really good video and fantastic explanation sir, can you please explain audio example record, playback voice control leds on /off .. really waiting for your reply and new video thankyou sir

[@Bwajster]

Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?

[@ardavaneghtedari]

Hello, Your videos have been amazing; but I haven't seen any new videos for a while. Are you still working with FPGA? Do you have any other websites or channels?

[@scientistterrific]

Hello Can you please help me in designing a digital clock project zedboard....please

[@leelaprasannadevadi9036]

Thank you sir, will you create one vedio for fsbl on vitis

[@asherpaul4450]

Can you please help us to have the Verilog code for calculating ifft and fft???

[@ravirajchilka]

Hi , can you teach me verilog? If yes please let me know

[@srikantachaitanya6561]

Sir ,Please do video on timing closure ...

[@angelg3986]

After fighting 2 hours with 'you don't have license for HLS synthesis for xcu15' I believe xilinx have not yet decided whether their business is to sell licenses or FPGA components.

[@raghub3090]

Sir, pls make a video on ethernet using zynq