How to choose PCB stackup?

[@rajgunaseelan44]

Thanks a lot sir. One suggestion. Please make more of these small videos, kinda like pointers from the long videos. I regret of not having the time to watch 1 hour videos loaded with useful information. Thank you so much again. Continue the good work ❤❤

[@Mike-ny5fm]

You still continue to be the best in explaining what I need to hear! Thanks Robert.

[@VaclavB001]

Very nice and explained a lot. After over 20 years of PCB design, I still find something inspiring in your videos.

[@Jorge-h5t3z]

Robert keep publishing good useful and mainly short videos like this one. You do a great job, likely improving people's designs.

[@MatthewHoworko]

Fantastic video, Robert! You present this important information in such an understandable way.

[@RelayComputer]

You already covered this in detail in many previous videos, and I have been applying this knowledge on my high speed designs. This shorter video obviously can't go deep into the reasons why these tips will improve signal integrity and reduce cross talk, but it makes a great job of summarising it

[@joeselvik9355]

Loved the short-form content! Would happily watch more of these over lunch.

[@anthonyk8027]

for 4 layer designs i use l2 and l4 for gnd planes. also i prefer only front side components mounting althougn it makes boards bigger. it’s kinda cool when the back side of the pcb is solid (no traces) and helps to radiate heat from bga chips.

[@karlOFuchs]

I have watched many of your videos to figure out how to pick my four layer stack up and came to the same summary conclusion shared here.

[@manouchehrmail]

Thank you so much dear Robert for this short but still very useful video.

[@pnrking]

Amazing details thanks for explaining 🙏🏻❤️

[@KofiAsare0]

Excellent info, 4 layers with 2 GNDs seemed like a waste until I looked at the oscilloscope results!

[@WindFaqeur]

simple and straight to the point!

[@haythem4766]

Thank you Robert for bringing up this point. Could you please create a tutorial where you explain how to perform SPICE simulations in Altium for crosstalk analysis and how to improve signal integrity using the SPICE tool?

[@melisasanag]

I learn a lot from your video's. Thank you so much.

[@AllenSharkY]

👍Very useful, thanks bro!

[@cedricb2344]

For decoupling at high frequencies having a big power plane very close to a reference plane gives you a big capacitors more effective than capacitors components at high frequencies. That makes 6+ layer pcbs much better for decoupling. I am not sure however about the best layer thicknesses on a 4 layers stackups when you have a power plane and only one full reference plane.

[@jortor2932]

Love you brother ❤

[@satoshimanabe2493]

Thanks for the great video! One additional advantage of thinner prepreg may be having a thicker core makes the board stiffer/stronger. This may be important in applications with high G-load. (i.e. automotive, model rockets) This makes me wonder: why do all standard 6-layer stackups have two core layers? It would seem a single core would be much stiffer. It could also improve signal integrity with a dedicated power plane, if you do something like S1-G1-S2-P-G2-S3, as all signal layers would then be coupled closely to ground. (With 2-core, S2 would couple more closely to P than G1.)

[@RobertFeranec]

I am not a PCB manufacturing expert, but I believe more cores means cheaper manufacturing - they can glue all the layers of the PCB in less steps. Also, during baking process, the layers can slide on prepreg and that may increase difficulty of building accurate PCB with too many prepregs ... maybe.

[@TheDutchGuyOnYT]

Very nice video Robert! I am currently busy updating my Pcb Toolkit app (iPhone) which I use while designing my boards and the current stackup function is not to my liking, because they change a lot and the manufacturers give a lot of options. Maybe too much sometimes haha. Your video gives me ideas about how to solve that.

[@shuashuashua1]

Thanks for next great video!

[@durgaprasadvishwakarma3298]

hi sir i have question how to charge and discharge one dc jack

[@316728237]

When 4 layer pcb, l3 used for power plane?

[@kumu2024]

Thanks. But talking about only pcb routing without mentioning that how big ground plains can also make your life harder is a miss. Using small BGA mixed with other bigger components while you have big GND will make your life much harder and you might fail measurably in mounting process in factory. Another thing that you should consider when you use fill area in to your PCB, components GND pin SHOULD not get bigger traces compared to other pins of the BGA. That could cause a big issue for mounting the component. Either you need to heat up the IC more than what it should be heated which can lead to short in those points. Or you will get cold-joints for the GND. I have seen that kind of design for (8 layers). They used Altuim designer to fill the are with GND. The tiny BGAs got their GND very big traces while the other pin were only small traces. We got often too much trouble to fix the heat-profile for the machine .. and either got short or cold soldering. There are much more to consider than only the signals.

[@TheDutchGuyOnYT]

Good point. There is never a one solution for all.

[@RobertFeranec]

Interesting. I have been using solid GND planes in all my PCBs (except for two layer PCBs) for over 24 years and I have only seen 1 serious difficulty in board assembly - it was when through hole pins were connected to 4 parallel GND planes and there was no thermal relief. Of course I have seen some components lifted up, but assembly house was always able to sort out everything. If anyone has materials on this topic, I would be very interested in making an interview video about it. Send me email to [e-mail] Thx

[@kumu2024]

@@RobertFeranec I am sorry, I cannot participated in that. The IC (similar to the MAX17050 in a WLP package) was used in several places, which made profile adjustments very difficult. The tiny BGA with 9 pins was challenging to mount, even for the machine. The designer did not consider adjusting the GND fill, resulting in a large trace for the GND pin, which caused significant issues. I mention this so that you and others are aware of it. Don’t let Altium or any other CAD program automatically fill your GND without verifying that it is suitable for mounting components, especially QFN and BGA packages.

[@RobertFeranec]

@@kumu2024 this looks more like a specific component / footprint problem which needs to be handled carefully

[@kumu2024]

@@RobertFeranec I dont think so. I had similar issue with other boards .. Combining different packages without taking in consideration of the thermal need of these components often leads to the same issue. But not many think about. Since it is a manufacturer problem than a designer in the first step. Often manufacturer tries their best to optimize the board-profile to match all these kind of diff components. But as I said, there is no profile that can save you when you have bigger traces and small tiny BGAs. Please think about that and ask other persons working in the manifestering processes.

[@xniyazi]

thnx

[@theondono]

The other day I had an idea that I'm not sure makes sense, but maybe you or someone else around here has tried. I'm building an analog sensitive current measure system (pA level currents), and I'm trying to reduce leakage current as much as I can. I've seen old references using PTFE based standoffs and things like that to reduce it, and I was considering if it makes sense to use a PTFE board for that purpose. Generally people go with PTFE for high frequency designs, so I'm a bit concerned if this really makes sense for DC designs like this one.

[@ergindemir7366]

I wonder why they don't make 3 layer pcb, it will be much cheaper and will work better than 4 layer for this configuration.

[@Jorge-h5t3z]

By the way 1080 stack-up is better, although price might be higher, not sure.

[@cedricb2344]

1080 has more weave difference in x versus y axis compared to other prepreg weave types.

[@Jorge-h5t3z]

​@@cedricb2344How important do you think it can be for a impedance controlled track over it? Do you have a percentage of impedance variation? I need to decide between both prepegs now for a 4 layer board.

[@cedricb2344]

@@Jorge-h5t3z see isola pdf on high speed stackups. Doesn't matter for most applications. 2116 and 3313 prepregs are the more uniform prepreg.

[@cedricb2344]

​@@Jorge-h5t3z See isola pdf on high speed stackups. If you can choose prefer 2116 or 3313 weave types with impedance controlled tracks. The difference is not big however.

[@Jorge-h5t3z]

​@@cedricb2344I was looking at the microscope pictures of that document also but a 90ohm diff track (USB example is 90ohm+-15%) over the 3313 is 150um wide, while over the 1080 is 125um. Only 25um difference. I will go with the more homogenous 3313 just in case, to be safer, but I agree there must not be much difference in the micrometric mesh of the 1080.