How to Decide on Your PCB Layer Ordering, Pouring and Stackup (with Rick Hartley)

[@marcov9581]

This is PCB design gold. Saving this to reference over and over again. Lots of great information and it's delivered in a way that is easier to understand than digging through all my books. Thanks for this!

[@Victor-Zaporotskiy]

On resonances in cavities and ground stitching vias. An analogy came to mind. It's like if you had a container with water. By swinging it back and forth with some frequency, you could easily achieve huge water oscillations. But. If you divided that container by partitions into many small containers, you wouldn't be able to achieve that huge water oscillations at that frequency. This is how ground stitching vias, by partitioning big cavities into smaller ones, prevent resonances in PCBs. Thank you, Robert, for your videos! They are extremely useful.

[@p_mouse8676]

They should teach this kind of stuff on the university. That's a thousand times more useful than most other things.

[@johnlocke3481]

When the professors haven’t been in the industry ever, and they wrote the text book they teach out of, that’s what you get 😅 Universities are so broken.

[@gustavrsh]

I'm graduating in EE and I haven't had a single PCB layout class.

[@p_mouse8676]

@@gustavrsh start making your own little projects!

[@gustavrsh]

@@p_mouse8676 Oh I did a lot of projects, but I never cared too much about EMC. I designed, programmed and flew a model rocket flight computer.

[@Aaron-lp3zt]

"let's plug these equations for an hour... oh btw do your capstone and design a board now!" great joke education, great joke

[@dreamofmirrors]

You have done so much for the PCB community. Thank you! And thank you, Rick! I do have a comment about routing high speed signals in the middle of the board (in order to get the power delivery near the surface). At speeds above 10gbit the via stubs will create significant problems (reflexions) which will require backdrill.

[@RobertFeranec]

Thank you very much. PS: I am planning to make a video about via stubs and backdrilling

[@優さん-n7m]

@@RobertFeranec the via stub length creates a reflection that can destructively interfere with the signal wave passing through it, basically the via stub looks like an open circuit and thus it reflects the signal back.

[@calvin-7540]

Awesome! This took me few hours to ｐａｕｓe and ｆａｓｔ　ｂａｃｋｗａｒｄ just for jotting down the super important notes.😍@@RobertFeranec I indeed learned more than I imagined! Thank you so much !

[@2_pence]

The most informative video on PCB design I have ever come across. You asked the right questions, and the guest was very experienced and prepared. This one should be included in the curriculum for any aspiring PCB Design Engineers. Thank you for the great work.

[@jeff-oi7cl]

My favorite guest, Rick Hartley!

[@RobertFeranec]

:)

[@Shubham-9996]

@@RobertFeranec This video are too long For beginners or not tooo much interested to study deeply Can you please Write vedios Summary in discription So we can understand what is advantages and disadvantages of topic Like here Putting gnd

[@guillep2k]

This is a very important job you're doing, Robert. It's great that there is now a good source for all the nitty-gritty details of designing a good PCB. Kudos!

[@mspeir]

I am so grateful that I found your channel! I'm a hobbyist with no formal education. I've learned so much from your videos. I've only ever designed 2 layer boards, but am about to start a project needing 4 or possibly 6 layers. I found you just in time! A lot of what you cover is over my head, but the principles are easy to understand and I'm better for it! Thank you!

[@RobertFeranec]

Thank you very much Mark for nice words.

[@ats89117]

Great video. Rick Hartley has really changed the way we think about EMI!

[@RobertFeranec]

Thank you ats89117. I am very happy you liked the video.

[@Reverend11dMEOW]

it has been awhile, aside from your channel, I clap my hands at the end, which is unreachable on far too many other channels! You Rock, Maestro!

[@lucabelvederesi6914]

Very very very very very and again very good! Thank you Robert and Rick, this video should be like a mantra for a PCB designer! And remember, the energy is... on the field!

[@RobertFeranec]

Thank you Luca

[@sameer_c]

You have done so much for the PCB design community and the people who are new to this that saying thank you would be an understatement now. Please keep doing the great work and teach people how to be a good electronics engineer. Love to Rick Hartley and you both ❤️.

[@RobertFeranec]

Thank you very much Sameeran

[@EPtechser]

Thank you Robert, for sharing this video conference with Rick. Even though I am not into multi gigabit designs it made me more conscious of the effect of fast rise times. Most of the boards I design are 2 and 4 layers and looking at this video made me realize I have to be especially mindful of digital signals with fast rise times on these low layer count boards and minimize the EMI effect. Thank you for that.

[@p_mouse8676]

I am the same, and this is why I always encourage people to still watch these kind of things. There is always something you can learn from it. I am also gonna change my work flow a little, first starting with rough layouting the board and second is to think about what stack-up I am gonna use and only after that continue with the rest of the layout.

[@ArnabMYT]

Thank you Robert. Your talks with experts like Rick Hartley and Eric Bogatin are videos that I visit every few months. Very grateful...

[@vejymonsta3006]

Incredibly valuable knowledge shared in this video. This will change the way I tackle my board stack-ups in the future, although I can't imagine I'll ever need to worry about such high density concerns. Definitely this should give me more confidence when I press the "place order" button.

[@larcomj]

I saw a similar presentation by Rick at PCB conference years ago. i was amazed then and still am now. Thanks for putting this up so i can re watch a million times =D

[@linqiang5734]

It is great thing that you bring Rick Hartley to the channel, Robert. I really like the wondering video about PCB Layer with EMI issues. Thanks you both so much.

[@kbeckmann]

Thanks again for yet another great video! I just want to say that I really enjoy hearing about bad examples as well as how to properly do it. The section around 30:00 is great, we learn about a misconception ("we need to shield the signals!" vs "the signals need a return path"), why it was wrong and how to properly fix it.

[@RobertFeranec]

Thank you kbeckmann PS: Very good point with "we need to shield the signals!" vs "the signals need a return path"!

[@Graham_Wideman]

... though I have a suspicion that "shielding the signals" (ie: preventing their electrical fields from escaping) is either the same thing as, or closely related to, "providing a return path" (for the AC current).

[@ravirajsingh4785]

I am a beginner in the PCB world and this video gives me LOT of knowledge about the LAYER STACK UP. Thank You for this video.

[@raulhernandezfernandez7859]

Thank you very much for your time and your video!! The title of my notes for this video: Print circuit board layer stack up (Gold dust)

[@RobertFeranec]

:D Thank you Raul

[@quanye4290]

Perfect Video about Stackup! It solved my confusion about Stackup and SI issues inside. Thank you Robert! Thank you Rick!

[@pablo_costas]

I came back to this video to double check how to handle a 4 layer stack up, nice material, thanks !

[@quickrd2095]

Now i Improved my all mistake while using (Ground AND Power) Plane onto 4 and 6 layer PCB... first i though it's don't matter or create EMI Problem if i select wrong Plane layer.. but i was wrong... i saw this video 3 times more for understand deeply.... Thanks you...you make my life...

[@niflheims]

I’m a software engineer but always have been attracted to electronics. I have worked almost 4 years with low level embedded (bare metal) code for a payment related company. Loved reading datasheets and schematics. Passively learned tons from it (by asking myself what I was looking at and why it was done like this). I had to move to another field but still do a little arduino like stuff in my free time. Always wanted to give Kicad a try, especially since I got into the rabbit hole of custom mechanical split keyboards. Stumbled on Phil’s Lab videos. Next on Rick Hartley’s and now yours. Love Rick’s explanations and stories. He clearly is the rickiest Rick 🙂 Anyway I’ve learned a whole lot of exciting stuff thanks to you all. Kudos.

[@soconnoriv]

i took a pcb design class last semester at berkeley as an extension student. Easily one of the most valuable classes i’ve ever taken. They knew I wasn’t an engineering student, but welcomed me in anyways. They taught me how to use Kicad pretty fluently. The cool part is that we assembled all of our boards by hand after we designed them and ordered the materials; the class is jam-packed full of hands-on knowledge. I took the class at night after work, the course code is EE-198

[@niflheims]

@@soconnorivthank you very much for sharing this info! I’m French so I personally won’t be able to attend it but it will probably be useful to others, so thank you. It must’ve been great to assemble your own boards, thus making everything from the (properly) ground up (bad pun, I don’t wanna be grounded). I love the idea of designing a whole object from the pcb to the casing and programming the firmware. Everything can be done with open source software, even FPGAs (maybe old ones but still).

[@victorbrooks3534]

Hi, Robert! Could you share with us the Rick's presentation on this topic? It seems to be extremely useful.

[@Tenus123]

@@VndNvwYvvSvv å

[@PrzemRS]

Robert, you always makes videos few days later when I'm asking myself how to resolve a particular problem :D Thx!

[@josebatistasales8272]

I have similar thoughts ;)

[@RobertFeranec]

I need to start recording sooner :)

[@ai5506]

this Q&A style is very helpful, I only understood it the second time Rick has explained if after your questions

[@gb7767]

Wow, incredible presentation ... thanks Robert and special thanks to Rick for sharing his vast experience on the topic.

[@johanragmark4189]

Great video! Your lessons and discussions are so valuable for me as someone just starting out with PCB design professionally.

[@nsknyc]

This is a magnificent video, thank you Robert. Rick's explanation were so easy to digest. Great job, both of you. "Robert: how can you simulate this... Rick: Good luck!" This had me laughing hard.

[@thomasyunghans1876]

Hi Robert, Excellent, thank you. Also, thank you to and Rick for sharing this information with us at no cost. Some have commented that the video is too long. I appreciate the discussion, even if it takes an hour or more, as the most important thing is to try and understand the concepts. Every board is different with different requirements and goals, and will require it's own set of compromises. Understanding the concept is the only way you can make those compromises intelligently.

[@MrKapludanger]

I was devastated when you jump 14 to 20 layer while i'm waiting hoping to see a design example for the 16-layer stackup structure towards the end of the video :D Luckily you exist and you are really teaching us a lot.

[@RobertFeranec]

I have not done so high number of layers PCBs, but I would expect them to be similar to the last two stackups ... a lot of Signal/Ground/Signal/Ground .... ordering

[@nameredacted1242]

What's the point? I can't afford anything above ~6 layers anyways for hobby, and the amount of time it would take to route 6++ layers would only leave this to companies and contracted professionals...

[@VndNvwYvvSvv]

​@@nameredacted1242Yes. That's exactly the point, lol

[@icestormfr]

Basically, pouring ground on signal plane can be a problem if you don't know what you're doing 🙃 For 4L board I put most SMD on L1 and r reserve L2 for GND (no signals at all) L1 for 90% of routing L3 primarily for power & secondary for GND reference of L4 (if possible) L4 primarly for GND and secondary for routing Final step: stapling all the gnd polygons with small vias 😅 So, basically, the 4L setup like (D) on slide 25, as shown 48:07 😁

[@RobertFeranec]

Exactly. PS: Also, sometimes pouring PWR instead may be the solution.

[@icestormfr]

@@RobertFeranec Yes 😁 And I just got now at the position of the video which corresponds with my strategy: 48:07 (slide 25, stackup (D))

[@icestormfr]

Anecdote: one time I had to fix a layout mess of a embedded main board ~A4 sized with 400 components. The colleague was nearly "finished" (his words) and was taking parental Ieave. I strongly suggested to him beforehand use a 6L (and go to 8L if he has problems)...he chose a 4L, the GND/Power situation was horrible (signals every layer, split reference pours, ...) And I just had 3 weeks to fix that due to deadlines 🙃 Couldn't go to other stackup, as it was already reserved in the pipeline of production. As all components were on top I deleted all GND/PWR, and used strategy above. First taking care of important power and high speed signals. Due to the via power and gnd tacking it resultet in probably ~1600 drill holes (before it was more like 600 due to many the pcie connectors) That was an interesting summer😅

[@RobertFeranec]

@@icestormfr Thank you for sharing.

[@josescxavier]

@Robert Feranec it would be great if you could elaborate a little more on 4L PCBs. If you have google examples to share.

[@nedarezaie5950]

this explanasions were fantastic. I had lot of question about why the ground vias are required next to the some signal and all are answered. I appreciate your time for creating this video to share with others

[@alexshei5061]

Thank you very much for this video. Watched it without any pauses

[@RobertFeranec]

Thank you very much Alex

[@dse-elektronik]

Hello, I've been designing two layers of protein since the program began. Thanks to your work and film, I won't be afraid to make the 4-6 layers I've been avoiding. Thanks to my movie buddy, he's as knowledgeable as you are. Greetings from Poland

[@RobertFeranec]

thank you dseszef

[@tr3547]

Federal. Such a great info packed interview w Rick. As usual. Took many notes. Please keep it up. I learn and relearn so much. Super fan, Todd.

[@randypeeters3931]

I will thank Robert and Rick for there great content. A lot of people can use this information. Thank you!

[@mjdevelops]

The result of the discussion was that the tracks of the power and the ground should be close to each other to neutralize their field? So that their field does not affect other signals on the board? My English is weak and this is how I perceived it. thank u🙏🙏

[@strictnonconformist7369]

Yes, I believe you understood the point, and if not, I’m in the same boat!

[@TimVT971]

Wow, Robert and Rick, you guys blew my mind. I was hoping that I wouldn’t see one of my designs in Rick’s sin bin. Thanks again

[@harryw489]

Robert and EEVlog are my favorite EE KZbinrs, but you two have very different styles...

[@harishrao2952]

Thanks alot Robert. You are providing such a valuable content. Listening to Rick and Eric always makes me learn something new about pcb design. Please try to comr with as much sessions as possible with Eric and Rick. Thanks alot for this valuabe information.

[@RobertFeranec]

Thank you Harish PS: I also learn every time I have a call with them

[@superciliousdude]

Yet another excellent video. This is one of the very few channels I enable notifications on, despite being subscribed to hundreds. :)

[@RobertFeranec]

Thank you very much

[@krzysztofsielewicz4161]

Thank you Robert! Amazing interview with Rick Hartley

[@RobertFeranec]

Thank you Krzysztof. I am very happy you liked it.

[@pgpiotrek101]

Wow! Thank you Robert. This was a great amount of knowledge.

[@RobertFeranec]

Thank you very much pgpiotrek

[@michaelk.1108]

Greeeaaaaat video!!! I love it!!! Thank you, Robert and Rick for sharing your experience!

[@RobertFeranec]

Thank you Michael for nice words

[@nielspaulin2647]

Really an expert! ... sorry I am from Denmark, but not employed in the mentioned company!

[@bukitoo8302]

Great video! TOO much information to process ! Thanks to Rick for sharing his knowledge!

[@RobertFeranec]

Thank you Buk :)

[@futuremax7]

48:23 for four layer PCB, I've got good information!! Thanks!

[@mrkv4k]

And that's why I like my 4 layer boards with ICs that have at least 5ns rise time. Anyway, thak you for very helpful video, I was always under the impresion that adding ground is pretty much always better, this makes much more sense.

[@Necrocidal]

I'm learning enormous amounts here. Thanks!

[@Ech01378]

Thanks so much, so much for sharing this precious knowledge!! It is not straightforward, considering the great amount of circumstances involved in PCB design.

[@RobertFeranec]

Thank you very much Emanuel

[@AngryMosfet]

This the video I've been waiting for! Thank you, Robert and Rick :D

[@RobertFeranec]

Thank you very much Bradley for watching

[@kentswan3230]

Great lessons in how stackup affects board performance. Thanks

[@Aemilindore]

Absolutely amazing content on signal integrity mate.

[@eid0eid0]

thankyou for this great interview. This video is now the new reference for the future when we have to decide number and order of layers.

[@ilyas.7209]

Perfect timing! Actually, it was so great it kinda became totally intuitive now. At least for microcontroller level stuff. Gonna go revise my stackup... By the way, glad to see Fedevel logo on the presentation slides :)

[@RobertFeranec]

I am very happy you liked it Ilya. Thank you for watching. PS: yes, I noticed that too :)

[@gabrielemarocco]

Thanks! This is a complete lesson on stack-up. Up to now I am not used to pour power on signal layers except near the input/output of voltage regulators or DC-DC converters

[@Jindraxx20]

GREAT video !! Thank you robert for making this happen and thank you mr.Rick for the information about layer stack-up and EMI problems!!

[@sagarnavale7856]

Thank you so much Rick and Robert for this wonderful session 👌👌

[@jaraleo]

Robert, this was great. Thank you very much for sharing this great talk! best wishes!

[@damny0utoobe]

Rick Hartley the man himself

[@ewafelber1658]

This is in my opinion your best video! It explains so many concerns about stackup which I had up to now and I would only hear some advises basing on "somewhere heard rules", which is very frustrating. Thank you!!

[@andreneves3597]

Hi Robert. What a great video. This is something that we do not learn on university unfortunately. Thank You

[@mata7648]

Layer number next the layer stack diagram will be really helpful. Excellent video.

[@RobertFeranec]

Very good point. I was actually thinking about to add them in post production ...

[@jamescullins2709]

excellent stuff, It starts me re-evaluating PCB design. Thanks, you guys are awesome.

[@soroushmoallemi774]

Thank you so much Robert and Rick for this great video.

[@STAR_Boy_6]

Very informative and great video, thank you very much dear Robert and Rick ❤🌺 Please post more videos of engineers' work experiences and how to solve challenges.

[@MatthewHoworko]

Great video Robert and Rick! Thank you for the great insights!

[@mdchethan]

Valuable technical information Robert, the questions asked to Rick were really good. Rick hartley was just awesome. By the way, I use the same 10L stack up which you mentioned in the video.

[@RobertFeranec]

Thank you Chethan

[@mdchethan]

@@RobertFeranec Also after watching this video, I am now very curious to watch your video on Flex PCB, I remember you have mentioned it sometime back that you are working on it. Hopefully we get to watch soon.

[@RobertFeranec]

@@mdchethan Yeah ... I have not had time to work on the FLEX project ... I asked friend of mine to help me with it .. he is also busy. So, it is on my list, I am just not sure when exactly.

[@PeskyNgon]

can anyone explain this to me please? @1:03:00 Rick says: "I wouldn't use FR4 beyond 4-6Gbps, 8Gbps tops. because the losses in the material beyond 4-6Gbps are going to be so high that youre going to have a sevear impact on signal integrity." This makes sense to me. But what they don't mention, is what the alternatives are. On sites like JLCPCB, the only options I see are FR4 or Aluminium. And Google isn't much help. So what alternatives do we have to FR4 for high speed designs?

[@dimonasua]

Oh, that was so interesting! Thanks for sharing this with us!

[@NitinPatil-dh2xl]

Hi robert and Rick, thanks for this video.

[@girishk7003]

This is very informative and simple to understand. Thank you so much.

[@thomasyunghans1876]

I am a little concerned about power/ground pours on congested signal layers which is suggested on many of Rick's stackups. If the layers are very congested, there will be many small islands and strips of poured copper which will require vias so they aren't floating. It seems like those vias might take a lot of room and make it difficult to route the signals. Maybe you would need to use smaller vias to minimize this routing congestion. If you have a dedicated power plane, you can just drop the power vias pretty much anywhere, but in many of his suggested stackups the power is distributed on all the signal layers with no dedicated power plane. In those cases, you will have to line up those power pours on multiple layers to get the continuity you need. Seems like that might greatly increase the difficulty of routing the board. Your thoughts?

[@鄭峻杰-i2k]

Robert, thanks for the sharing. Actually I got into problems on stack up design like how to arrange planes order and how to determine it exactly. I received heavy info form this video. Thanks again.

[@artrock8175]

The PCBWay add prior to the video was actually pretty rad!

[@montvydasklumbys7584]

Cannot thank you how much I appreciated the video! I was watching all of your videos and they each add a slightly different perspective. I would actually really wanted to see some video where you design of a PCB with 4/6 layers with the in video suggested stackup, since it is a bit difficult to fully imagine how this should be routed: ----- Sig/PWR ----- -------- GND --------- ----- Sig/PWR ----- -------- GND ---------

[@DiegoColl44]

Very nice video..!! Thanks Robert and Rick..!!

[@myhobbies5965]

Always excellent topics and videos, thanks for sharing such a great knowledge.

[@Porama6400]

I do appreciate the message that we should do simulation on high speed signal. unfortunately, it will be a long time till those simulation price come down enough for hobbyist to afford.

[@RobertFeranec]

I agree .. the software is not only expensive but also it is not easy to run and understand simulations.

[@muhammadAli-uy5fi]

very interesting talk by Rick!

[@RafayelGhasabyan]

Thank you very much for the great video! In the customer problem described starting from minute 35, the solution is given by pouring copper on 4 layers and connecting them either to VCC or ground. However, it was also mentioned that the customer did not agree to change the layer stack and add more layers. My questions are: 1. If adding layers is an option, would that be a better one rather than pouring? 2. Is there any disadvantage in adding another 2 or maybe even 4 layers having signal and ground separated, except the cost?

[@di987654321]

in 1:08:00 12 layers board- What about the control impedance in Layer4, if we want signal with control impedance of 50 ohm who is his refernce plane?

[@Tabu11211]

I am no where near this level of design but I feel like one day maybe I will remember this when I need to x'D

[@A4R2F0]

The video was awesome, Thank You and Rick so much ❤️

[@RobertFeranec]

Thank you very much Alireza

[@juanmanuel8464]

Thanks!

[@RobertFeranec]

Juan, thank you very much for your support! PS: I wish youtube would email me about Super Thanks comments.

[@tradegrabber4854]

Great lecture, thanks Robert!

[@rahulkumar-bf4cq]

Awesome I liked this most and extremly useful. Thanks to both .

[@ssonerboztas]

Very very nice video, thanks a lot for these very important informations Rick !

[@pcbworks]

Thank you a lot Robert and Rick

[@Fusion12345]

Filling vias with peanut butter sounds tasty 🥜 19:40

[@gsuberland]

I've heard Rick use that example so many times now, and it never fails to crack me up :D

[@RobertFeranec]

:D

[@ilyas.7209]

I have a related question: Main power of my device is 5V (most current use), I also have several ICs, including the MCU itself, that run on 3V3, LDOed from 5V. The chips talk via 1MHz max SPI via level shifters 3V3-5V (if there is a voltage level mismatch and 3V3 signal is not enough for 5V device). MCU is 50MHz max - down to under 10MHz, but I have yet to scope stuff to see the rise/fall times. PCB is 4 layers. Have analog/digital parts, analog measurements and digital communication never occur simultaneously. I have a prototype PCB come soon, and since I didn't know all this at the time, I have basic caveman SIG-GND-5V-SIG without any pours, while 3V3 is routed via traces, I try to make them wider. Space is not much of an issue. But now I understand I can improve it significantly. Before I do something I regret, I'd want to clarify a few things: I'm (re)considering stackups now, PCB is expected to be 1.6mm thick with thick core: Stackup Option 1: Sig/GND 5V ------ GND Sig and 3V3 routed as traces. This will let me couple signal more to GND than to 5V, so I should get better performance, at least comparing to what it was before. And, of course, stitching when swapping signal layer? Alternatively, I can have polygon of 3V3 Power, larger polygon of 5V power on a single layer, like Stackup Option 2: Sig GND ------ PWR (polygon 5V, polygon 3V3) Sig/GND I'm worried about having different voltage polygons. As far as I understand, I should then split the components and put 3V3 and 5V components separately. And a corner for analog stuff. I also understand, I'll have to do some stitching between layer 2 GND and layer 4 GND. What do I do about level shifters, which utilize both voltage levels? Where do I place them and how don't I mess up their return currents? I mean, it makes sense to put them between the polygons duh, but what if not? Another question into the same basket: If I have multiple polygons of different voltages and I don't have anything cross the gap, maybe a thin GND pour between 5V and 3V3? Why or why not? Maybe couple 5V and 3V3 with capacitors? Don't hit me if I said something stupid, after all, that's why I'm asking) Also, as an active EE stackexchange user, I asked a pair of questions there, and while I got some advice there, the general consesus was "your design is too slow to care about these things too much". To what extend is this true? Of course, it's good that I know about those things and consider them anyway. My first prototype was 2 layer with signal spaghetti - both layers ground pours, and it seemed to work, but I still want to do things right and not get used to improper amateur designing. EDIT: maybe layer 1 can have signals AND polygons of different voltage, while 2 is GND, 3 is GND, 4 is Signal? I will have to run a few power traces, but I guess it will work? It's a stackup 3 options being created right here as I'm editing this post. Why/why not? I'm kinda leaning to Stackup 1 for now, but it's purely intuitive and not reasoned enough in my head to be sure about choosing one stackup over another. P.S. I still haven't decided what stackup I want, in either case I'll have to start the PCB from scratch I think, and I'm OK with that (it's fun anyway).

[@ilyas.7209]

I have decided to go with the following stackup: 1. Sig (90% of signals, 100% of components) 2. GND Solid plane THICC CORE 3. PWR +5V Solid plane 4. Sig/GND (tightly stitched) (10% signals, 0 components) I routed 3V3 with traces, optimized my design enough to have literally 3 components to need 3V3, so traces seem ok solution - and I have two linear 3V3 regulators, one dedicated for SD card, so that it doesn't cause interference with 3V3 MCU when it writes/reads/suddenly consumes power. Since I do some analog with MCU, I added ferrite bead and two 0.1uF to MCU's only power pin. Analog in one corner, digital in another, high drawing element (display) away from both and is close to Power circuit not to cause interference. Routed SPI and UARTs in the first place, then analog, then many single-ended signals like ENABLE which are OK with switching layers. Added extra GND VIAs where I switch signal layer from 1 to 4 to keep good referencing. Analog in North-East, Digital in the South, Power system in the West, High current display connection North-West.

[@Neuroszima]

for me stackoverflow/stackexchange isn't the best place to ask anymore, but it wasn't due to my personal experience, rather others - with the infamous "moderation problems". I only look there for help with programming troubles. EE knowledge i get, i get from EEVBlog forum. This post is also one that could be asked there on that forum, not really under some comment on YT, especially having so many questions.

[@ZongyiYang]

Hello. For a two layer board, is it better to have signal+power pour layer and a ground plane layer, or a signal+power traces with a ground pour layer and a ground plane layer? From the slides around 50:20 it seems like the latter is selected as the improvement example? Is there a difference?

[@Reverend11dMEOW]

THANK YOU SO MUCH! This, though skyscrapers taller than my education so far allowed previously, "that said" all by itself brings me to a MUCH DEEPER understanding of the big picture here. ", having said that," is the 2020's replacement for "ummmm". ;-)

[@wmcmick]

Thank you so much for doing these videos, amazing value! :)

[@RobertFeranec]

Thank you MickGyver for watching the videos

[@michajarmuch6305]

Great video! I usually use 4 layers PCB. I'm interested in watching how the PCB from 45:55 looks like. How to design signal track from SMD components when on the TOP and BOTTOM you have ground plane? Do you have some example? It will be great to see how create PCB in this way.

[@RobertFeranec]

Thank you Michal. PS: I was actually thinking the same

[@Graham_Wideman]

Well _obviously_ you put the components on an inner layer :-) Seriously, I think the idea is you can still put the (SMD) components on the top, and flood ground around them, but instead of signal traces on top, the component pads connect to very nearby vias through to signal traces on an inner layer. This way, instead of the via inductance being in the ground network, it's in the individual signal nets, where there's perhaps less current and also more series resistance anyway. Rick mentions this at some point where he describes an already-designed board, and moving the outer layers to be layer 2 and N-1, and in that case the traces already avoided traveling under the pads (that were left on the outer layers) and thus were able to accept adding vias easily to connect the signal layers to the pads (I guess). I'm not sure if he implied vias near to the pads, or vias-in-pads.

[@SKNGL]

Robert... me too thinking how the layout has been done with 4 layer stackup. Very curious to know types of signals in that pcb.

[@VndNvwYvvSvv]

​@@Graham_Widemanyou joke, but in very rare cases, you can do this with a cutout. Probably have to solder those ICs yourself though.

[@sajinm7625]

Thank you very much Robert Feranec for this video. Please work more on topic like this, it is really helpfull for me. Can you share the slide that you were using in this video, that will be a huge help?

[@RobertFeranec]

Thank you Sajin PS: I do not have the slides. But you can take screenshots of the important slides and place them into a word document. That could maybe also help.

[@sajinm7625]

@@RobertFeranec sure I will try to do that, and share to you as well

[@DavidMcCurley]

Excellent video. Very informative

[@eliseomoran7388]

Awesome information. Congratulations.