How to Design RF Trace Tapers (With Free Calculator!)

[@stephenjbro]

Excellent video. The amount of resources you're putting out for RF circuit design is great.

[@AltiumAcademy]

Thanks so much!

[@arijitdas1884]

Hello Zach! Thanks for the video! Hardly ever thought that even optimal taper length can be analytically calculatable 😅, will take that as a learning. So far the idea has remained to be that to stretch the taper as long as possible for a given allowed space.

[@Zachariah-Peterson]

Yeah I think it is surprising that you can calculate a useful length, but if you think about it the taper has an input impedance, and that input impedance is a function of the signal wavelength. If the wavelength is much longer than the taper then the taper would appear invisible, just like any other impedance discontinuity.

[@arijitdas1884]

@@Zachariah-Peterson Yes agreed. Probably this is one of the few instances when very high frequency came out as a relief 😅

[@javierguevara7773]

Excellent video, as always! Could you make a video talking about the rotation of the PCB to mitigate the skew due to weave glass discontinuities. I am doing it for the first time and i am not sure about the process, if i have to rotated the PCB within the designed panel or if the manufacturer can rotate the laminate.

[@Zachariah-Peterson]

Great question, yes I'll add it to our queue

[@ranknis]

This video provides valuable educational content, and I truly appreciate it. Thank you for sharing such helpful information. I have a question regarding impedance matching: I need to match an input impedance of approximately 1 kilohm to an output impedance of 50 ohms. Do you believe that I can achieve this using the Excel file you mentioned? Your assistance would be greatly appreciated. Thank you.

[@Zachariah-Peterson]

The calculator is only for matching between traces of different impedances, it is not intended for matching impedances generally. This is because the trace width defines the trace impedance, but a high impedance value such as you reference might have no relation to pin size or pad size used to connect to the trace, so most likely modifying trace widths coming into a component will not give the desired level of impedance matching.

[@mdd7359]

Thanks for another great video. When you were trying to calculate the wavelength of this 3GHz signal (at about 16:00), you used 3 as Dk value. Shouldn't sqrt(3) be used in the calculation instead?

[@petersage5157]

Shouldn't it be possible to design a connector and footprint such that the specified impedance (50 ohm, 70 ohm, 300 ohm, whatever) is maintained from cable through connector and footprint? An Industry Standard on this would greatly simplify the implementation of board-to-board connections; connector impedance shows up in parametric searches, footprint can be copied from datasheet, standardized transitions from footprint to board traces are standardized, Bob's your auntie.

[@Zachariah-Peterson]

I'm not aware of a standard specifically on board-to-board connector footprints, right now you have to call out things like ground cutouts in a datasheet, or the designer needs to simulate it themselves. The other thing is that a problem is that you can't put polygon cutouts in internal layers in footprint data because they are stackup-specific, maybe you can do it with a keepout. So unfortunately there is a bit of disconnect between footprint data, CAD tools, and what is actually needed in the footprint when it comes to RF connectors. But to be honest it might not be the best idea to put that kind of object in a PCB footprint just because the cutouts required depend on multiple factors like the board thickness, any coplanar routing present around the signal pin, etc.

[@Bob-zg2zf]

🎉

[@gopichand612]

Sir can you tell me length matching tolerance equation

[@Zachariah-Peterson]

Are you referring to length matching between the traces in a differential pair? The equation is based on the allowed timing mismatch between two signals, and this is based on the rise time of the signals. As long as the two signals in a differential pair are switching at the same time, then the differential receiver can recover a logic state from the differential pair. So this means the length tolerance is equal to the rise time tolerance multiplied by the signal velocity. The best timing tolerance to use is the receiver's timing skew limit, which is often found in datasheets. You can watch more in this video: kzbin.info/www/bejne/gpXUq3WYa5WcbMk Note that it is best to try and get as close as possible to matched lengths on long routes. This is because random and deterministic skew both accumulate along the length of the differential pair. With random jitter you cannot control how large the timing mismatch will be, even when the two traces are the exact same length.