How to do STA Hold Timing Analysis ?? Learn @ Udemy- VLSI Academy

[@vnnmichael]

thank u sir. Understood v well

[@ashishsrivastava6269]

in Hold analysis weather the phi (clk -q +combination delay ) also include setup time .

[@snehilrathod2322]

If the edge is same to evaluate the hold time, and as you said gitter doesn't matter for hold since its the same edge. Then why do we still have to consider the uncertainty (HU)

[@palanisamy7665]

how to rectify hold time violation.. as you said for setup time by increasing clock time??

[@VLSISystemDesign]

Hi Palani You can add buffers in datapath or all clock buffers in launch clock path. Also, increasing clock time for setup time is the last option to resort to. Ideally, you should be trying to fix setup time without increasing clock period

[@palanisamy7665]

thanks for your valuable reply!!!!

[@singaluriram]

Thank you sir

[@VLSISystemDesign]

You are most welcome Vijay

[@ashishsrivastava6269]

if setup time is mux 1 delay and hold value is mux2 delay then sum of mux1+mux2 is clock-q delay ??? if yes i have timing report file in which i have i have setup value 0.352 but clk-q delay 0.120.

[@tausid979]

why pulse at zero nanosec reaching at both flop in case of hold time analysis

[@CopyPasteGrow]

in setup time we analyse the problem at two different time instants. We analyse like "let's at t=0 if launch flop is sending some data then what will happen at t=T at recieving flop". I am taking ideal scenario here. and for Hold analysis we analyse both ends at the same time i.e. at recieving flop we are analysing previous input which was given at t=-T. So we are analysing "what is happening at both the flops at the same instant of time."

[@kshitijsingh131]

thank you sir