How to do STA Introduction To Slack And Hold Timing Analysis?? Learn @ Udemy- VLSI Academy

[@srushtikadam1514]

After watching like over 15 videos over 3 months, I finally got the feel of understanding hold time!

[@karsonify]

What you described as the hold time is actually the clock to Q time. The hold time is dictated by the fact that the clock edge is not an ideal step but rather a linear rise causing some the D and Q to be "transparent" for a short time. During this the output of the Launch flop should not reach the Capture flop else shit happens

[@mattchen3298]

+karma sonam I agreed with wat u have been said. The hold time for the ideal CLK for this flip flop should be 0.

[@kcpractronics9371]

Sir, Thank you for your presentations.... in the above video there is a fault in the "Hold time" definition... the delay of MUX2 has no effect on the Hold time.. becoz when ever the +ve clock comes the MUX1 gets disabled and if there is a change in the input 'D' it's not going to affect the circuit in any way... as the MUX1 is disabled from input 'D'during 'logic1' so, the Hold time doesn't depend on the MUX2 delay rather we should consider the "Clock path delay" too in describing Hold time.

[@JoaoPSCerqueira]

Great video. Thanks!

[@akankshajambhure2742]

Sir,what if we apply same rising edge to both flops for setting time?

[@thedmutz]

Great video series. Thanks

[@shivakc49]

Thanks Ghosh.Please share some tcl interview questions.Thank you

[@ParadiseQ]

Should we consider clock-to-Q time in the analysis?

[@ajaykumarmukka5409]

Hi, skew is (capture - launch) or (launch - capture).

[@MrPumatube]

ajaykumar mukka , it should be capture - launch according with the definitions of positive skew and negative skew

[@taazanranjan129]

sir can you provide me the pdf of given topic also

[@AMANKUMAR-oh1zt]

bhot late ho bhai.