Clock Gating | Integrated Clock Gating cell

[@srilakshmipeteti8087]

Excellent Explanation!!!!!! thank you so much the concept was evident...

[@federicomoro8690]

You have just save my life. I was making a ring counter with flip flops and I had the problem of full propagation because propagation time was lower than clock time. I have add a d latch enabled with ce and neg clk between each flip flop and now everything works.

[@lakkisai2257]

Omgg!!! How simple and easily you've explained

[@ankittripathi4939]

It was such a beautiful and smooth explanation. Extremely good work. Worth watching.

[@chinmaykaul7746]

Same adjectives to be used from my end. Thanks a lot

[@nalinikeshavamurthy3052]

Very nice explanation .it would have been better if the ICG working was explained with waveforms when negative level latch was used .

[@SumanTanwar-y2b]

Thanks Jairam :) This is a very helpful video :)

[@rajavikrampullem7583]

Superb explanation bro...

[@pavankalyan_varudu1515]

such a clear and neat explanation ...thank you so much

[@aradhanakumari4029]

Wow very detailed and well explained video. Great work. Keep it up

[@jairamgouda]

Thank you

[@jayaramank3236]

great pls upload more video for better understanding for all the topics

[@eshankanoje249]

Very detailed. Thank you for making this video

[@harshatpant]

Thanks for the video. Do you have one discussing the timing requirements for the ICGC cell? Even with the negedge latch, the enable cannot be toggled very close to the posedge of the clk.

[@carterlee287]

How does a Clock Gating implement in RTL? And How to take care of Clock gating in STA?

[@soumyajyotipaul4915]

could you explain why the AND-Latch ICG that you showed is reliable when driving pos edge FFs only ?

[@nandithasuresh]

Hi Jairam, in the last slide, I am not able to get the 3rd point about the negative edge where the Enable signal is captured. Can you please explain that a little more?

[@jairamgouda]

Hi Nanditha, can you please check my reply to the same question in the comments asked before? I've replied to Ayushi Dube

[@nandithasuresh]

@@jairamgouda I still have some doubts.. Question: Can you help with a figure explanation so that it is clear to me? I am confused between the logic that generates the enable signal.. I am constantly referring to the last but one slide, and trying to relate..

[@jairamgouda]

@@nandithasuresh please note that I haven't shown how the enable signal is being generated. And that depends on the design parameters. ICG won't have that logic as well. Logic that generates the enable signal is beyond the scope of this topic. I'll try to make a video on that. But for now you can imagine it as a divided clock or generated slower clock from the main clock signal.

[@nandithasuresh]

@@jairamgouda Ok sure..

[@ranveerdhawan744]

Why do timing paths with enable pin of ICG cells fail after CTS?

[@alectaylor4273]

Not the best explanation but better than my University Professor so well done

[@rejilrajep3641]

Great video jairam. Have one doubt . Isn't it a better way to notate dff input as enable instead of output?

[@ayushidube6478]

can you explain last point of the video in detail?

[@jairamgouda]

Sure Ayushi, what I meant was, enable signal comes from some other logic gate. And enable also needs to be a low frequency signal than that of actual clock. That logic should be intelligent enough to make sure whenever needed it supplies the clock and when not needed it should turn off. So, that logic also needs clock and it's also controlled by clock. Usually those logic will be pos edge ones. If it generates signal at pos edge, then it has to be caught by the neg-edge triggered flip flop is the neg adge of the same cycle. So, it has just half cycle to do so. If it's the low sensitive latch it can catch it any time when signal is low. So, gets almost full cycle. Hope it makes some sense.

[@ayushidube6478]

@@jairamgouda thnku! i understand more now...

[@merrygo7189]

Can you make a seperate video on mother and daughter cells ?

[@jairamgouda]

Hi, I will try my best to make a video on this topic as soon as possible. Thanks for your support.

[@merrygo7189]

@@jairamgouda sir ...I found this is one of most interesting topic ....this type of pg cells used in evry ono design....i didn't find much more in Google therefore I asked to make video on PG cells....your videos are quite easy to understand....you have used more technical terms ....

[@jairamgouda]

Hi Merrygo, take a look at the video on power gating and mother and daughter cells that i just published. Share your comments. kzbin.info/www/bejne/hWerq3mrhL2pf8k

[@merrygo7189]

@@jairamgouda I will share in this video in my group

[@abhishekvashisth8314]

good video

[@saivijayabhaskargade1528]

thanks a lot bro

[@chokkakulasatish9624]

thanks very benfettied out of this video

[@alterguy4327]

ಧನ್ಯವಾದ

[@ayushibhardwaj93]

Thanks 👍

[@denisethorbjornsen7493]

resistors lower voltage.

[@ashutoshmishra1068]

well explained but try to use simpler Technical terms many novice try to understand and face difficulty

[@jairamgouda]

Sure Ashutosh. I accept your suggestions. Thank you very much for your support.

[@ggulddung]

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