How to Set Up a Crosstalk Simulation | PCB Layout

[@saeidesekhavati1518]

Thank you for making this video. It was very helpful, please create more videos on shortcuts and tools about Altium Designer.

[@dimonasua]

You have to call this video "Hidden Gem in Altium #2" :)

[@bernard.tomasevic]

Where’s #1? :D

[@dimonasua]

@@bernard.tomasevic kzbin.info/www/bejne/i52ZpH-KbdqWgas :)

[@sirdapplton]

@@bernard.tomasevic it was a video featuring Eric Bogatin about Altium's built-in 2D field solver for impedance profiles

[@lsfornells]

Contrary to what you said in 13:45, over termination does not create new reflections as far as I understand. It will create slower rising edges and thus longer propagation delays, but not any new signal integrity issues

[@Zachariah-Peterson]

I should have clarified this, for a series resistor you would see the new reflection on a backward propagating wave since that arises from the new impedance mismatch you created from overtermination. But looking in the forward direction with an excessively large series resistor, you are right you will see a slower rise time looking towards the output. Since the simulation is not looking at any backward reflected wave you can't see what that reflected wave looks like.

[@iPatroni]

I get [Fatal Error] Crosstalk Analysis.in Signal Integrity Unexpected error occurred in simulation when I try. Running the latest version. Do you share the files in the demo? I could check if it's something I'm doing wrong.

[@sattarmonjezi4396]

Zack, thank you very much!

[@petertwiss356]

Termination is a hard requirement for DDR, it is part of the DDR specification. So is timing (net length matching, arrival times of nets).

[@myetis1990]

Thank you Zach for the great video. I would love to see how an IBIS model is created from measurements (a really good skill to achieve ).

[@Zachariah-Peterson]

I may have to get Ben Dannan on to help explain that because he has much more expertise than I do. Still a really good topic so I'll have to set it up.

[@mz9zn]

On 5:00 you measured a distance between centers, it's not the same as spacing...

[@malamian1]

Great topic! thanks.

[@AltiumAcademy]

Glad you liked it!

[@gabrieltovar1235]

Hi Zack great video like allways. Would it be possible to have the demo design used in this video?

[@balajiprasanth6287]

Cross talk related there is no point of termination right. only will use impedance matching purpose right please clarify here how impact termination at near end cross talk.

[@zaferacun3314]

Hello, Thanks for video. Why can't we see 3.3V, 1.8V or 5V when the signal is defined in the 1n, 2n or picosecond ranges in the signal integrity tool? In general, waveforms come out at 700mV, 800mv levels. Is there a limit on the signal integrity tool? In the video, when you lower the start, stop and period values in the signal stimulus section, the signal voltage dropped to 900 mV. What is the reason? Is it related to Altium's computational limits?

[@Zachariah-Peterson]

Great question! This occurs because the time between the rise time and fall time was set very short. In one of the examples the time betwee the rising and falling edges was set to only 500 ps, so the downward edge of the stimulus was being triggered before the stimulus voltage value could rise to its full strength, that's why it did not go up to full scale.

[@zaferacun3314]

@@Zachariah-Peterson Thank you Zach for your response. I have one more question : In the waveforms at 16:29, I saw that the crosstalk peak to peak at the source was higher than the crosstalk peak to peak at the Target. Actually, I would expect the opposite. I would expect less crosstalk at the source and increased crosstalk towards the Target. Why is more crosstalk seen in the source? And Which values should I enter to give 5GHz Signal for start, stop and period?

[@Zachariah-Peterson]

​ @ZAFER ACUN I think this is because the falling edge just happens to coincide with the valley in the underdampred response in the crosstalk waveform, so the crosstalk induced on the falling edge superimposes on that waveform. Let me think about it a bit more and maybe this will be clear. For a 5 GHz signal, if you're talking about 5 GHz being the data rate, start and stop would need to be spaced out by 200 ps. To simulate a 101010.... bitstream then you would want to use a period of 2*(1/(5 GHz)) = 400 ps. If 5 GHz is your bandwidth, then the rise time will need to be some fraction of the unit interval (UI). Something like 20% (or 40 ps in your case) would be typical.

[@zaferacun3314]

Actually, this is a 10Gb/s high speed interface, I found the bandwith 5 GHz and the Tr from 0.35/5 Ghz to 70ps. However, I could not get the rise time as 70 ps in signal stimule. Whatever value I enter, I get the lowest 700ps rise and fall time of the signal. I was going to ask if there is a lower limit on the tool's calculation for rise and fall time. Can we simulate signal integrity in Altium for signals in the GHz range? How can I define start, stop and period for this example?

[@iPatroni]

Very interesting, thanks.

[@AltiumAcademy]

Very welcome

[@SivasankarSaravanan]

hi how did you created that microprocessor and DDR first ? its confusing

[@Zachariah-Peterson]

I did not create these components, I accessed the CAD data for these components in the Manufacturer Part Search panel in Altium Designer. You can access many components from this tool. If you can't find a component you need, then you can usually find the schematic symbol and footprint from a 3rd party data provider. The other option is you can make the CAD data yourself.

[@walterma84]

Hi Zack, Thank you very much for making this video. We found that Altium supports only IBIS models up to V5.0 (specification from 2008). Unfortunately a lot of manufacturers are providing their IBIS models in V5.1 or greater. When will Altium support a newer version of IBIS models? Thanks!

[@Zachariah-Peterson]

I know that earlier versions (I think AD17) supported v5.14, that should still be the case. It would be odd to find that the newest version does not also support the newest IBIS specification, but I did not see information in the Altium documentation after a quick search.

[@vedhachalamj810]

Hello Zack, this content is very interesting to simulate crosstalk, but the SOIC packages pin is not suitable for 3W Rule, eg: Pin width is 0.4MM, Spacing between next pin is 0.254MM, Its make crosstalk?

[@Zachariah-Peterson]

You do not need to use the 3W rule in every design. The 3W rule is overly conservative and was developed at a time when everyone was using boards with thicker dielectrics and no ground plane, both practices are not appropriate for modern designs. You should learn to use at least 4-layer board with thinner dielectric below the surface layer. For example, if you use a standard 4-layer board with 4 mil dielectric below the surface layers, then a microstrip would need about 8 mils width to have 50 Ohms impedance on the surface layer. With the standard pin pitch in JEDEC specification for SOIC package, you would have about 50 mils center-to-center distance, or 42 mils edge-to-edge distance. This satisfies the 3W rule anyways, but with 4 mil dielectric thickness to the trace you will be able to violate the 3W rule to some extent.

[@87Spectr]

thank you very much!

[@AltiumAcademy]

You're welcome!