How to simulate PCIE / IEEE path on PCB + Everything you need to know | Explained by Bert Simonovich

Setting up simulation and explaining everything essential you need to know about channel simulation such PCIE or IEEE. Thank you very much Bert Simonovich
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Chapters:
00:00 What is this video about
00:53 What is channel and why to simulate it
06:33 Why is loss important
14:25 Stackup
15:21 Dielectric properties Df Dk
21:47 Copper roughness
27:34 Construction tables and stackup
33:05 10 layer stackup example
38:30 When start worrying about stackup details
48:03 Copper Roughness models
57:53 Filling up Stackup into Polar software
1:03:53 Setting up Dk and roughness
1:06:46 Calculating Loss of a transmission line for stackup in Polar
1:09:05 Saving model of transmission line
1:20:29 Creating models of VIAs
1:33:20 Dielectric anisotropy
1:38:52 DesignCon
1:42:41 Creating and setting up simulation
1:51:11 Simulation and results
1:54:04 Comparing good and bad PCB material results
1:57:28 COM - Channel Operating Margin
1:59:07 Setting up COM simulation
2:02:57 COM results
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It is much appreciated. Thank you,
- Robert

[@bertsimonovich7297]

Thank you for having me on your show Robert!

[@RobertFeranec]

Thank you very much Bert for your help with this video

[@myetis1990]

I've learned a lot, sir thank you for the great presentation. I would love to see more on such topics.

[@DS-vu5yo]

What I love about your channel is even though you know much more than most PCB designers, you ask questions like a complete child. No pretentiousness. It is incredibly valuable for us that are trying to suck up as much as fast as possible. Please always keep asking “dumb” questions. Because all of us dumb people need the answers. I’ve learned more about pcb design from your channel than any other source hands down.

[@RobertFeranec]

thank you very much for watching and nice words

[@MrMah123esh]

Very informative!

[@DS-vu5yo]

Regarding Dkx and Dky: this is a rare case where the orthogonal EM coordinates and the orthogonal physical coordinates are NOT the same. You should use Dkx and 45 degree Dkxy to model the complete solution. Dkx and Dky will only vary by the weave parameters. Dkx and Dkxy will vary on maximum difference in bulk material properties.

[@bertsimonovich7297]

All glass reinforced laminates are anisotropic. Dkxy and Dkz are effective permittivity of the dielectric when measured by a particular test method. Dkxy means the electric fields generated by the dielectric test fixture are in-plane or parallel with the fiberglass weave, while Dkz the e-fields are out-of-plane or perpendicular to the glass fiber weave. When an EM wave propagates along a planar transmission line, the e-fields are out-of-plane with the glass weave so Dkz value is needed to model Zo. When an EM wave propagates through a via, the electric fields are in-plane so Dkxy value is needed. Dkxy and Dkz are merely simplified naming for in-plane and out-of-plane values for permittivity.

[@anthonyk8027]

so pity that it’s hard to watch on mobile device, i don’t mean phones, i mean tablets. on my ipad i constantly zooming to see what is going on the screen, so small symbols there.

[@martinvasilev9809]

Grat vid! Very important stuff were sead and i lernd a lot. Thansks! ❤ I have one question around 1:30:00 we see a TDR of the VIAs. I did not understand where/how do you set/determen the rise time of the exaitation impuls?

[@bertsimonovich7297]

In ADS via designer TDR viewer tool, the rise time is set automatically based on the maximum frequency simulated. In this case it is 20 ps.

[@deepblue6564]

Cool!!!

[@biswajit681]

Hi Robert please make video on Analog and power supply design

[@dongolahmed]

EEVBLOG has already done it

[@tambui8367]

@@dongolahmed you can share link with me. Thanks