How to Synthesize Verilog HDL in Quartus Prime (OSU ECE272)

Created to help students in Oregon State University's ECE272 Digital Logic Design lab learn how to synthesize Verilog HDL into logic using Quartus Prime Lite.

[@jacobfield2214]

Note: You should probably actually use SystemVerilog, not Verilog like I used in this video. There are minor differences that could cause issues copying the SV code directly from the book, so you could run into errors if you use Verilog instead of SystemVerilog.

[@ssupertutorial]

hey how is your ptoject on the commutacar citicar ev car going?

[@jacobfield2214]

I no longer have it unfortunately! I got it running with salvaged batteries from a Nissan Leaf and toyed around with it for a while. I sold it before moving to college since it wasn't practical to keep or use as a daily driver. I posted a lot of the updates on instagram on @explosive_golfcart