How To Use the SignalTap II Logic Analyzer Tool in Quartus Prime

This video is created by my student Shawnna Cabanday. The tutorial is based on Quartus Prime version 17.0 using DE1-SoC board.

[@pepapu7112]

Thank you so much!! This video is more than helpful!! Our prof just task us to use signaltap but never taught us how to use it...

[@guillaume8437]

So useful! Thank you! By the way, I used the SOF manager to flash the sof file on the DE SoC board, not the device programmer but it will be the same...

[@guillaume8437]

Rania Hussein, is it normal that every single time I try to change trigger conditions and/or add/remove nodes to analyse the system asks me to recompile? Moreover, it proposes to make a "rapid compile" but the button "rapid compile" is not clickable...

[@Blutharsch]

This video was great, thank you!

[@_AmHam_]

You helped me a lot ! thank you Rania! Chokran :)

[@raniahussein4974]

Amin Hamdi You’re welcome. Best wishes

[@daysirc]

Best tutorial! (than the useless and outdated of intel r_r) do more please :)

[@kulasekarans5428]

I'm using a DE0-nano board. When polling some registers in Signal tap for debugging, the register's name appears RED in color. I don't know what it signifies. If it appears in RED, then the register's value stays at zero. But, if I assign the register to an output port, its value changes to black and it functions as it is supposed to. But I have unwanted ports in the bdf now. Can anybody tell me what the RED color actually signifies and how can I fix it? Thanks in advance :)

[@varadpatil369]

We are facing the same issue, how did u solve it

[@mohamedlarbibouchellal6037]

Thank you, hope you ll make more of FPGA tutorial !!

[@paulspark7287]

I would love to see a tutorial on trigger conditions and storage qualifiers. I have been trying to capture signals between certain states of my state machine (e.g. start capturing on one state and stop capturing on another state). You would think this would be simple to do but I haven't managed yet. Intel's training videos are so dry and don't show good hands-on examples like you have done here.

[@raniahussein4974]

Paul Spark Thanks for the feedback. Will take your suggestion into consideration.

[@leandrokeenzapa2217]

very helpful!

[@nandoperu100]

Thank you for explain

[@kavingaupulekanayaka222]

Thanks lot for the simple and nice demo about the signal tap analyzer. I'm using Arria 10 GX PAC and I want to use signal tap analyzer. However, in my case I can program only to PR region using fpgaconf bitfile.gbs (not a .sof). And then using the SW API, I need to trigger the run. Signal tap analyzer always show "program the device to continue" even though I already programmed using .gbs. Any clue would be helpful, thanks.

[@raniahussein4974]

Kavinga Upul Ekanayaka I haven’t worked with Arria 10 GX so cant comment on that. Sorry

[@m8111806]

If you get invalid JTAG error, it must be due to .sof file. Go to top right section where it says SOF manager, then click on ... and locate the path for .sof file.