FPGA & SoC Hardware Design - Xilinx Zynq - Schematic Overview - Phil's Lab #50

FPGA and SoC hardware design overview and basics for a Xilinx Zynq-based System-on-Module (SoM). What circuitry is required and what to pay attention to (decoupling, configuration, voltages, sequencing, pull-ups/pull-downs, etc.) when designing more advanced hardware. Example design for Xilinx Zynq XC7Z007S System-on-Chip (SoC) in a CSG225 BGa package. Including multi-voltage buck converters, DDR termination regulators, DDR3L memory, QSPI and EMMC memory, and more!
Mixed-signal hardware design course: phils-lab-shop.fedevel.education
[SUPPORT]
Free trial of Altium Designer: www.altium.com/yt/philslab
PCBA from $0 (Free Setup, Free Stencil): jlcpcb.com/RHS
Patreon: / phils94
[LINKS]
Avnet MiniZed: www.avnet.com/wps/portal/us/p...
Zynq Pins: www.avnet.com/wps/portal/us/p...
GitHub: github.com/pms67
[TIMESTAMPS]
00:00 Zynq Introduction
01:19 System-on-Module (SoM)
01:46 Datasheets, Application Notes, Manuals, ...
02:40 Altium Designer Free Trial
03:01 Schematic Overview
04:40 Power Supplies
07:50 Zynq Power, Configuration, and ADC
11:47 Zynq Programmable Logic (PL)
14:14 Zynq Processing System (PS) (Bank 500)
15:32 Pin-Out with Xilinx Vivado
17:52 QSPI and EMMC Memory, Zynq MIO Config
19:05 Zynq PS (Bank 501)
20:16 DDR3L Memory
22:55 Mezzanine (Board-to-Board) Connectors
ID: QIBvbJtYjWuHiTG0uCoK

[@damny0utoobe]

What I like about your channel is that whenever I'm thinking about some design (zynq), you likely come out with it in a few weeks.

[@PhilsLab]

Glad to hear our designs seem to be in sync! :D

[@MommeSherif]

Same thought 😂

[@AndersNielsenAA]

This! XD

[@Eldon_Dice]

I don't think you realize how your videos are helping us jr level engineers get through the first years of industry grind. I spend my free time watching your videos and others. I really appreciate your insight. More SOC videos please, really interesting.

[@PhilsLab]

Thank you very much for your comment, Edgar. Very glad to hear the videos have been helpful!

[@Eldon_Dice]

@@PhilsLab No, thank you for spending your free time on making these videos, apart from your full time career -- not easy. Your work is high quality.

[@jordixboy]

as a self taught software engineer, with a decade in the industry, also thanks! I dont work in the electronics industry, but I do it as hobby, because learning is fun! thanks

[@vatsan2483]

This series is highly looking forward to learn more about the layout and design in pcb!!

[@xThirdOpsx]

This content is golden, thank you so much for taking the time to putting it together. I will be soon supporting you with a purchase on your courses.

[@PhilsLab]

Thank you very much - very glad to hear that :)

[@tuloca011]

Great video as always Phil, thank you for making complicated topics accessible to us!

[@PhilsLab]

Thank you, Renato!

[@mohamedtebbo6095]

Can't wait to see part 2 , where you do the layout of it !!

[@Cracked1ce]

Great video! I design with the Zynq RFSoC and MPSoC at work and this was a great refresher on FPGA circuit design. Also a very good selection on your power supply IC.

[@PhilsLab]

Thank you, Daniel!

[@ajays886]

thanks to you phils , I will start my hardware design .

[@AD-lk2nv]

love your work phil, brilliant content as always. been keen to design my own FPGA board at some point so this is great.

[@PhilsLab]

Thank you very much, hope you can get started with FPGA design soon!

[@rick_er2481]

Thanks Phil, already looking forward to the layout & routing video!

[@PhilsLab]

Thanks very much, Rick!

[@igorb4650]

Whow, an awesome job on getting trough schematics and reasoning behind it!

[@PhilsLab]

Thank you, Igor!

[@professorstabsalot]

This is outstanding! I am hoping you do a segment on PCB routing for the DDR.

[@largepimping]

I am never doing any of this, but I still find it very interesting. Another big "thank you for making this"!

[@PhilsLab]

Thank you very much for watching!

[@tim21010]

This is just perfect! I have a course with an introduction to zynq this semester and just started designing my on SoM (for the XC7Z010-1CLG400C) last week. Keep up the great work!

[@PhilsLab]

Awesome! I actually also previously did a design with the XC7Z010 (same package you are using) but saw these were in stock and immediately bought them. Good luck with your SoM!

[@mth469]

have you got anywhere with it?

[@xy3986]

Zett-Brett - einfach genial Phil- mach weiter so !! 🙂🙂🙂🙂🙂

[@PhilsLab]

Danke dir! :)

[@kushalkumarkasina9862]

I can't thank you enough for making this video.

[@PhilsLab]

Thank you for watching!

[@shauni_jade]

I literally started a subject at university on this yesterday, what a timing

[@angeldavidcastillocastro7816]

Excellent job my friend.

[@PhilsLab]

Thank you!

[@Bianchi77]

Nice info, thank you for sharing it :)

[@mekbots7607]

amazing ,please more of this

[@PhilsLab]

Thanks, more to come!

[@JasonFritcher]

As you get further with this series, are you planning on doing any videos on the PL design for the FGPA portion of the SoC? I'd be highly interested in seeing that, as a continuation of the hardware design.

[@nicoladellino8124]

Very impressive project 👏 👏 👏

[@PhilsLab]

Thanks, Nicola!

[@TheWhatnever]

Awesome! Im very curious about the DDR Routing. It's what kept me from designing my own board and using an SoM instead. Also I'm very curious of your background in in this topic. Because even with an SoM, teaching myself everything until Board Bringup was a crazy learning curve.

[@rjordans]

This looks promising, looking forward to your next episode! You got me curious about the limiting elements in kicad though, looks like the new version has a lot of improvements in that regard

[@PhilsLab]

Thanks! I've yet to try out many of the improvements to KiCad 6, would be interesting to see how a design like this would fare there.

[@yamanseyravan4387]

Perfect Work, i would love to see how to program those kind of systems !, keep the good work !

[@PhilsLab]

Thanks! Videos on that topic will be coming this year.

[@kamagongchannelofficial]

thanks for sharing

[@PhilsLab]

Thanks for watching!

[@maxhouseman3129]

Great content! I think the most difficult thing is to program this fpga. I did that for my master thesis and it was crazy (I have 10 years of programming experience).

[@NivagSwerdna]

Perfect. This is the sort of stuff that interests me... although on a slightly smaller (Lattice ice40) scale.

[@PhilsLab]

Thank you!

[@CSFitness1]

Awesome video, just started putting together schematic for my Zynq based SDR platform, more or less for the same reasons as you; to learn and say I can do it from the ground up. I started with the same approach as you grabbing all the datasheets and app notes, but eval board designs are invaluable (lots of slight variations to pay attention to). Looking forward to the layout video!

[@PhilsLab]

Thank you, Chris. Hope all goes well with your Zynq-based design. Did you manage to secure some Zynq chips? IIndeed, eval boards are incredibly helpful as well when doing these kinda designs.

[@CSFitness1]

@@PhilsLab yeah actually buying chips right now should be interesting…. I’m just gonna design to a certain variant and hope for the best.

[@danriches7328]

Looking forward to the serpentine traces on the DDR3L ram and how it compares to how I've started / starting routing a 12Gbps 4kp60 HDI interface, couldn't come at a better time!! Thanks Phil!!

[@PhilsLab]

Awesome, looking forward to making a video on it. Thanks for watching, Dan :)

[@uav.project8022]

Exellent job. Do you planing finishing sensor fusion series?

[@XxEm202020xX]

Do you plan on making any videos on programming/HLS with Vivado/Vitis? Looking forward to the rest of the series!

[@PhilsLab]

Yes, will be making programming videos once I have this board in my hands + the daughter board.

[@babington77]

Hi Phil, More great content as usual. Thanks for taking the time to put this online. Really looking forward to see how you route this typically difficult Xilinx design onto a PCB. I know you will probably use Altium, but do you think it would be doable using KiCad?

[@PhilsLab]

Thank you, Tim. Definitely do-able with KiCad, however probably more of a pain in the neck than it needs to be, so yeah - I'll be using Altium.

[@johnferrenby7486]

IF you make full course on SoC PCB and Programming(Verilog/VHDL and C/C++), I will BUY that course.

[@damny0utoobe]

You can't fit all of that into a single course. PCB, HDL and C++ will be their own courses. If you do try, then it ends up being a diet course which wouldn't be useful. With that said, I would purchase a series.

[@dekev7503]

@@damny0utoobe you're right. He might as well ask for him to make a complete Electrical Engineering masters degree course.

[@oraszuletik]

Nice!

[@PhilsLab]

Thanks, Ger!

[@TheGhost13X]

Will you finish the control design course sometimes? Thank you!

[@mohamedtaher6262]

Great work 👏 👏 👍, can you give us the altium project ?

[@obregr]

intetretin as always

[@PhilsLab]

Thank you, Gregor!

[@vailotok5727]

Hi Sir, where can download this Altium schematic file? Thanks, so cool.

[@mth469]

Where can we get your schematics so we can follow along, sir? Preferably in PDF format. Thank you!

[@brokenicry]

can't wait for the layout video, as a professional PCB designer

[@PhilsLab]

Thank you!

[@mth469]

i want to try doing a board design with this Zynq chip as a noob. I have some experience doing PCB design with stuff with pins. But nothing with BGAs. Am i crazy?

[@greglaletin]

Wow, I was looking at the same reference board to make my own som for a quadcopter but can’t find the time to burn on it. Look forward to seeing how it turns out. Just from this video I know I would have stuffed up the ddr.

[@PhilsLab]

Yeah, the whole design is pretty time-consuming. Let's see if everything works at the end of the day :)

Hi Phil, where did you get the symbol for the XC7Z007S? If you made it yourself, can you do a video on how you reliably make such a high-pin-count symbol without taking decades entering each pin from the datasheet? Thanks

[@bennguyen1313]

Do you think the Avnet Ultrascale+ eval boards, would be a better choice than the older Zynq boards (MiniZed, Trenz ZynqBerryZero, etc)?

[@rajimordecai1099]

Thanks my guy. Can you do more explanation on DDR interfacing to processors/FPGAs? I'm always confused with the data, address pins etc. Or point me to any link to learn this.

[@PhilsLab]

Thanks! Yes, will make a video on this when I have the finished board in my hands.

[@joanlopezjimenez8336]

Hello, SoC programmation is the real future? it would me mandatory to learn about it? Certainly, its awesome.

[@anilsuha5301]

Oh oh ohhhhh 😍😍😍😍

[@piotrkaminski3443]

What i like to do is instead of just "listing" subsheets in the top level sheet i create sort of block diagram using sheet entries. This way it's easier to see how signals are connected between each sheet.

[@Mr_ASIC]

give kicad some love

[@samba8579]

i want to ask one thing.. how to generate .bd file from schematic diagram?

[@pasblo39]

One question, do you create your own components in Altium designer or do you use a component library? If the latest is true, which one?

[@PhilsLab]

I usually create my own symbols and footprints. Altium Designer has an IPC-compliant footprint wizard which is really helpful.

[@pranavmokashe1637]

Design files available for download?

[@theonlyari]

Damn! This is a deep one! I really like that this isnt meant for the hobbyist group- not that theres a problem with that, but theres enough of that content already on youtube. I noticed that you didnt mark your diff pairs with the diff pair parameter. Is there a different way to do this in Altium?

[@PhilsLab]

Thank you, glad to hear that! Yeah, I hadn't marked the PL pins as diff pairs yet, as I'm still undecided how many of them I'll be making single-ended or differential.

[@anilsuha5301]

What's the density of Emmc and Qspi flash ? Can't wait a video about pcb.... I believe there will be 2 videos of pcbs one is only preparations and design rule settings and another one will be routing? 😍Thanks Phil

[@PhilsLab]

Thank you, Arun! I have several implementation videos for DSP content. The process for the PID controller is very similar.

[@anilsuha5301]

@@PhilsLab Phil..... I'm a big fan of your work. You put soo much effort and the outcome is really good. Thanks for all the knowledge. And yes I've seen all your videos.

[@MommeSherif]

We really could use u in our company! Man! Good work! If u r interested I can talk to my boss, we are in Hamburg and Kiel!

[@RafaelVieira-wx9ux]

when it comes down to fpga programming, do i need to care about eletronics? isn't it always only logic gates and hardware description languages? im new on the field

[@johnferrenby7486]

There are not many courses or books online on how to do SoC with simple explanations. Like where to click, how to setup basic stuff. They all go for advanced stuff right away

[@johnferrenby7486]

especially on How to Treat SDRAM/DRAM with SoC

[@Slicomful]

That is a nice jump. From simple mcus to complex fpga) I love it! I have to take back the comment I left on last video. Please make a video of routing, not just showing the result. Result is not interesting, process is much more interesting) Thanks.

[@rick_er2481]

The whole process would be great indeed! The whole tought process etc

[@PhilsLab]

Thanks, Alex. I'll probably show aspects of the routing but not the entire process as that would take many, many hours.

[@guruG509]

Can you do a video on DFT?

[@PhilsLab]

Might make a video on the FFT in the future.

[@jack_brooks]

Can you go over the costs associated with software development tools and IP needed to be purchased to do this SOM? These costs can be extreme in low volumes, and the vendors don't make this info clear. They just assume you are going to buy everything.

[@PhilsLab]

Vivado is free and supports (most) 7-series FPGAs/SoCs without an additional license. Won't be needing any paid IP for this design. So software development brings no costs with it so far. The PCB manufacturing + assembly costs in low volume will be quite substantial however.

[@jack_brooks]

@@PhilsLab I only have experience with Altera products and I have to work on a zero dollar budget. DDR3 IP was not free with the free version of Quartus (at least at the time, I don't know about today), so I was limited to old SDRAM in my designs. Because I have zero dollars to work with, I end up using cheap eval boards as SOM's. But everything is going DDR3, so even that doesn't work because I couldn't use the memory without getting a paid Quartus license. I was assuming you needed to use a paid license of Vivado to do what you are trying to accomplish.

[@mth469]

the schematic meistro... if you please.

[@franzliszt3195]

So many capacitors in parrelle. Why not just one bigger one?

[@PhilsLab]

Physical placement on the PCB, close to relevant power/gnd pins.

[@franzliszt3195]

Yes, but why 4 caps next to each other? Wouldn't one on each end be enough? Thank you for the reply.@@PhilsLab

[@PapuavTronics]

Can you please create a paid video course on how to create this fpga SOM on Udemy or something, Please. I really want to learn how to design a SOM fpga.

[@PhilsLab]

Yeah, my plan is to create a course on FPGA/SoC-based hardware design. It won't be on Udemy I'm afraid but rather on Fedevel Academy.

[@PapuavTronics]

@@PhilsLab Thankyou so much Phil

[@Narindersingh-ss7pb]

Har har Mahadev

[@perceptron9834]

I the past you did a lot with global labels now you are connecting all elements direct to the MCU. Why did you change your mind?

[@tomaszkluska6419]

Jednak AMD a nie Intel. Bardzo dobrze.

[@PhilsLab]

True - however, I think I'll still be referring to these as Xilinx for a while :D

[@tomaszkluska6419]

@@PhilsLab Always :)