HWN - "SoC Design Engineer" Interview Question (Offsets)

Hi fellow (and future) engineers!
We polled our KZbin community and the ninjas have spoken! Analog IC design it is. In today's video we will understand a bit better how a seemingly simple question can be explore at any depth level depending on the candidate's experience. We hope you enjoy the content!
Welcome back to another episode of Hardware Ninja! Ever wondered how to get a job as a Hardware Designer in some of the top tech companies like Microsoft, Google, Tesla, Apple, Facebook, etc?
The interview process employs many application based questions whether you're a recent college grad or an experienced applicant. It doesn't matter if you want to work for Elon Musk, Tim Cook, or the up and coming start-up you heard about. We're here with curated material of real life technical interview questions.
Please consider subscribing to the channel and supporting our movement. Prospective job seekers (including yourself some day) will benefit from this resource.
LinkedIn: / hardware-ninja
Reddit: / hadwareninja
Twitter: / bytor_hardware
#analogelectronics
#cmos
#vlsi
#vlsidesign
#designengineer
Background Music Merry Bay - Ghostrifter Official
/ ghostrifter-official

[@xsirfr1958]

I think a better answer is to distribute the same reference voltage to 4 op-amp controlled current mirrors circuits. If you have 1 input: 4 output type mirror as you suggest, you will be limited in accuracy due to Vth mismatches in the FETs. If the reference is relative to GND, then the parasitic IR drop in the GND needs to be made the same for all 4 blocks.

[@HardwareNinja]

Great answer, Robert! Op-amps will also suffer from offset problems as well as take considerable area/power. What you mentioned about the grounds is really important, you'd most definitely need a ground re-referencing circuit for each of these if we choose the op-amp route. We very much like your answer as it shows a different approach and showcases your problem solving skills! This is at the heart of interviewing. Thank you so much for being a part of the community!

[@coolwinder]

Point: Use currents for phisicaly seperate devices.

[@fuckkatuas2837]

The problem with this is that the PMOS also needs a supply voltage. Is the source of the PMOS tied to the same Vsource?

[@HardwareNinja]

Hi Katuas, Love the first name! If we understand your question correctly, you're talking about the PMOS devices at 5:08. If that's the case, since that block is a bias generator, all the PMOS devices are in close proximity as matching is crucial here. We only send their output currents as information. Let us know if that's what your question was about. Cheers!

[@jiesteve]

So how do you regenerate the voltage ref at the destination blocks?

[@alperkurt100]

You should use same type of resistor according to your process at the destination block. Incoming current will flow through the resistor and it will regenerate the same voltage. These can be done with using bandgap reference. For instance, bandgap reference block will generate appropriate VGS for the current mirrors. These currents will be carried to the destination blocks and thanks to same type of resistor that we used in bandgap reference circuit voltage will be regenerated. Here same type of resistor is very important so that we can regenerate same voltage for PVT analysis. Note: You can use LDO block in order to regenerate the same voltage somewhere near to the destination blocks if you want to filter the noise and increase the PSRR response of the circuit. This will be significant for the destination blocks that needs very clean VDD.

[@HardwareNinja]

Hi James, The reference voltage is produced by the Vgs of a receiving diode connected device. This Vgs can be different at every corner of the IC. However, since we're sending current, even if the Vgs voltages are different the mirror currents will all be the same. We hope that made sense. Let us know if you still have any doubts!

[@jiesteve]

@@HardwareNinja I though the problem statement was to distribute a VREF into the receiver blocks.

[@jiesteve]

@@alperkurt100 ok so this method you need to assume the far apart resistors are matched and you can also have a delta between bias generator ground and the receiver ground, right?

[@HardwareNinja]

@@jiesteve You're correct, the problem statement is to distribute a voltage reference to each of the 4 corners of the IC in such a way that they're all biased identically.

[@ninjanuggetsbrozhaf441]

I have an interview next week for my intern and i dont even understand any of this😢😢