i got asked this question for my nxp interview! and solved it thanks to you. Sadly i didn't land the internship

I wonder if really 95% fail

A pass gate to match the delay of inverter

Isn't a question of IR drop instead ?

We can also ask about the slew rate of the amplifier from the interviewer. Since Vout is changing from 0.99V to -149V instantly..

I did the simulation, it seems that it does indeed pick a lower current, but is not a very good system, as evaluated it is off by a factor of 2 when the current are equal. I don't think bob was wrong, but i don't think this is analysis is wrong either. The difference in current will have to large for the system to work, so it works under some conditions.

Why Isw increases after t0 instead of decrease? Because Isw = Iin + IL(KCL), and IL decreases over time after t0.

If this is an overlapping seq detector you only need s2 states. S2->S1 on a 1 output 1 or S0 for a 0.output 0.

You are cute..

God bless you

We can’t say anything cuz we don’t know from where we are getting the current and where it ends

Was the answer a Dff?

We can also use Millers Thm to arrive at the result

Thanks for uploading these lecture series with that high quality. I was wondering if you could upload the rest of the lectures as well?

Thanks, I've been shortlisted for Optiver FPGA Intern Role Can you please guide me with the topics I should revise for the Interview

The solution is vc(t) = 1-cos(w0t) where w0 is the natural frequency given by the expression 1/sqrt(1LC) .

Is the Hardware/IT technician job market growing or shrinking? Or has it been stagnant

Like the videos would love if there be more or a concise part 1 and part2 as I dwell on it ahahha

they steal berkely's ee240's copy right and mix with their copied slides.. If you are in US, this is gonna be fun in court

The solution and explanation is incorrect on so many levels Ninja. Verify your concepts and then upload videos. College students will learn and remember false basic concepts. Please Take care.

great video, did he ever upload the solution to its following question? How do you design the circuit?

what would happen if Vin becomes 0 again? Will the Vx ramp down to 0 at exponential decay while the Vout ramps up to 0 at linear rate?

it wont saturate because of capacitor rating. It would saturate because of the limit of current source. If a capacitor has voltage rating, it might get fried.

A faster way is to assume input impedance is high (so an open circuit) and output impedance is low (so basically a short). In that case we are looking at the resistance of 3R in parallel with R + 2R which equals R/2.

I liked the white background better over the blue check background - just saying :P

You would use the buck converter as you won't have as much wasted power do to LDOs burning the current and kind of acting like a regulated voltage divider

"promosm" 💕

I want to join your team and contribute to the community.

Amaizing, thank you very much for this great contribution. (Hy from Argentina)

Is this considered an analog design question?

My answer to produce the symmetric waveform: . . . . . . . . . I would use a transmission gate always fully on (pmos gate to gnd and nmos gate to vdd) so that its intrinsic R and C will delay the signal as the amount of delay we need. Then add on both sides a couple of inverter to regenerate the signals out of the TG. Otherwise we could use a CPL gate which can produce a differential signal starting from the single ended one without TG and the one inverted. What do you think about it?

🤯🤯🤯

interested in other solutions

Guys I have an interview at Qualcomm tomorrow please wish me luck

Yes please explain the other possible answers and effects in a seperate video!

Interested in other possible answers

last

I would have asked, gate voltage referred to what node ? GND ? Drain/source ?

All W/L on tape out IC😅 I see it all p+N w/L on the ic When you do design and it needs be matched on frequency, (N+P all C effect )

Much appreciated 😊 Such as sw,vx,iL,isw waves ...❤

Pass P_MOS+Err amp +Vref+2 resistors+Add capacitive coupling at the input and output ends 🤔

I have an interview next week for my intern and i dont even understand any of this😢😢

How you arrive at your answer, the thought process, the assumptions and how you communicated those to your team mates are more important than being right. The best answer is arrived at when the team is in sync with each other. IC Design is a team play. I thought the circuit presented was a current modulator i.e. I2 modulates I1. Varying I2 varies VDS1 and I1 will change slightly due to channel length modulation by VDS1. But i enjoyed listening to your thought process.

berkely's ee240 2010's version remix ?

I understand where "Bob" is coming from. Not saying anyone is right or wrong, but depending on the biasing will totally change the way the circuit behaves...including different than the description in the discussion.

For the Vout curve, shouldn't it decrease from 0 to -Vcc with an RC discharge profile rather than a linear downward slope (since this is an active LPF which would slow down any sharp edges such as a step at the input because they contain high frequencies). Please let me know if my understanding is wrong or if I missed something that makes the Vout drop linear instead of an exponential decay/RC discharge profile.

Please make an explanation for Asynchronous FIFO as well.

You’re being tricky so I’m going to be tricky with you back as an absolute strict hard definition without having given Measurement points or additional input output to the circuit outside of what has been drawn then strictly speaking without diagrammatic sample points it’s series/parallel until further notice, of course that has absolutely no meaning without local resistance measurement, therefor what you want to use it for becomes the relevant question.

Earlier it was one fail remaining off & low brightness Now it is one fail remaining on & high brightness