Inference vs Instantiation vs GUI tool in FPGA

Learn the differences between these three methods of creating blocks of IP (Intellectual Property) or Cores inside of your FPGA. They are inference, instantiation, and using the GUI tool or IP generator.
For the text version of this video: www.nandland.com/articles/inf...
Help me make more videos! Support me on Patreon!
/ nandland
Practice your FPGA skills with some great hardware! Get yourself a Go Board:
www.nandland.com/goboard/intr...

[@ThePriyavrat]

High standard explanation! I was looking for this. Thanks!

[@GR7Media]

Thanks very useful for my projects!

[@saranyasampath1383]

All your videos are great..!! you are doing a very good job...Your explanations are clear and understandable...looking forward for system verilog,it would be great to learn from you..!!

[@uwezimmermann5427]

good explanations, easy to follow your style, but you should use a slightly larger font size for your code.

[@Nandland]

Yeah you're not the first person to mention this! I'll fix on future videos, thanks!

[@Ganjin88]

I find in vivado. When I use the GUI to create a Block Ram.... it somewhat gives me an idea create how to instantiate a particular BRAM (ex: RAM18E1). I think I'll stick to GUI and Inference. As long it gets the job done right? But I appreciate this video. I'm learning on creating RAM using VHDL through the FPGA. I'll have to eventually learn Verilog but not now.

[@ntesla66]

Good work! Have you thought about a few videos going over component instantiation and port maps in VHDL vs the same component instantiated in Verilog? Say just a simple shift register? Say three identical components clocked together and how this would be done in Verilog vs VHDL, not just the code but the (how and why)/differences of the two hdl's. What are your thoughts on SystemVerilog?

[@Nandland]

I hadn't thought about that. I did do "VHDL vs. Verilog" but was trying to do a fresh take on it, rather than comparing the two languages at that level. But it's something I could go back to. I really like SystemVerilog a lot for testing. Actually I like it so much that I will use it for testing my VHDL code. I haven't talked much (any?) about it yet as I've been focused on the standard VHDL/Verilog stuff for beginners. But perhaps some day.

[@brianwang5660]

Hey Russell! Great video. I was wondering, what happens when your WIDTH and DEPTH parameter exceeds your FPGA's BRAM size? Can that even happen?

[@Nandland]

You should consult your FPGAs datasheets, but depending on the specific size your synthesis tools will cascade BRAMs together to allow for larger configurations.

[@brianwang5660]

@@Nandland Thanks Russell!

[@peterhalverson929]

Is block ram preloaded with data possible with the inferred method? The instantiation method gives you that ability but as you explained its tricky to use and not portable.

[@Nandland]

Yes it is possible. Make sure your Block RAMs are capable of being preloaded. Some FPGA fabrics are not (e.g. Microsemi).

[@peterhalverson929]

Thank you, I'll try it.

[@eminakgun4301]

nice explanation but better if you explained the way how that code infers a BRAM Thanks!

[@Nandland]

Yeah sorry, I could have explained that more. Basically the synthesis tool "sees" a large memory and knows that it can push it to either A. Flip-Flops or B. Block RAM. So it will choose Block RAM if it's large (usually several hundred bits is enough to go to Block RAM).

[@eminakgun4301]

I was thinking that the actual reason is we are trying to write or assign data at a rising edge when a condition occurs and we are accessing the output data at a given address no matter what. Then the tool understands that this is what exact behaviour of embedded BRAM hardware? Is that true?

[@Nandland]

@@eminakgun4301 Yes that's basically it. The tools see that there's a large memory, a read address, a write address, and it knows how to create a BRAM out of that.

[@Jonas_Meyer]

Which of the 3 would you use for SerDes? Gui?

[@Nandland]

I've used both the GUI tool and direct instantiation for SerDes. I think the GUI would be the preferred approach.

[@gamenetworks2016]

Can you explain it in VHDL code or any link? I need help.

[@382946rthu]

System Verilog would be better 😉