Architecture All Access: Modern CPU Architecture 2 - Microarchitecture Deep Dive | Intel Technology

[@LeleSocho]

Hey this was incredibly produced and clear enough for many people to understand, you guys should publicize it more because i stumbled upon it almost casually.

[@hariranormal5584]

When a actual Microprocessor company makes a video UNDERSTANDING how they work? Heh, and for the fact this actually isn't made bad. Don't get me wrong other content in KZbin that explain this sometimes can be easier and maybe harder. But I actually am amazed Intel really is doing this

[@masch4]

@@hariranormal5584 absolutely

[@GregoryJones9038]

Honestly Boyd Phelps did an incredible job with these two videos. Granted I've been around since the 486 days and have always had an understanding of the various CPU architectures, but this was incredible with it's depth.

[@tuongnguyen9391]

I want intel to make more technical video like this. The more the better, I have a genuine interest for the inner working of the product instead of just buying it and wish for larger caches , better features.....As a customer , I really love your dedicated effort of creating a highly understable video with good analogy

[@bgtubber]

I love this series! It's incredible how these devices even work without a hitch given how mindbogglingly complex they are.

[@glenwaldrop8166]

What's really amazing is they don't run without a hitch, there is an acceptable error rate that they recover from. That is part of why systems are more stable today than previously, more threads, more cores, if a thread crashes it doesn't take down the entire system. It's not just at the CPU level but errors still exist they just don't take down entire systems as often.

[@karenkomeh737]

)l

[@kilman54]

I don't normally thumbs up or comment on a video, but, when I do, it's because a channel has done something really amazing and I want them to continue!

[@ThunderingRoar]

The editor needs a raise

[@JJsTechEsports]

Incredibly well done, breaking down such a complex topic into chunks that are digestible isn't easy and you guys did that super well!

[@adinchandra1797]

First time I have Phone, Internet access and Social Media, I started Addicted to all about Technology Especially about CPU

[@platin2148]

I would look at posts from fabian gisen and agner

[@user-eb6vc2gs9e]

This means you know who is George Boole

[@MadamLava094]

This was actually incredibly well put together! I always found that nothing really would ever bother to explain how exactly the subcomponents of a CPU talked to eachother, but this really helps show how a CPU is a lot of smaller, specific-purpose modular pieces talking to eachother

[@perburr]

This two-part series is brilliant! The animations have blown me away! So clearly explained, without patronising the viewer. If the animator ever reads this: you did a fantastic job on this video, very well done.

[@fernandoayala876]

Having had the opportunity to be at Intel for years (no longer there), so proud to see these series coming up. Very well done, something rather complex explained in a simple form. Hope that entice and nurture the imagination and curiosity of everyone, especially younger ones!

[@kcvinu]

Lots of information with high quality content. Great effort Intel !!! And the host is doing an amazing job. His way of teaching is marvelous. For the last few weeks, I was searching for the topic "Computer architecture". Since, I am a hobby programmer, I would like to know more about how CPU execute my code. Thanks a lot for this series. :)

[@alexandrebustico9691]

Love it. Explanation on branching and speculative execution is great. We must emphases that branching is the key of turing completeness which permit the birth of computer from previous simple calculator.

[@Umeldaraje]

I am in chip design from 1984 and tried many times to explain to people what am I doing. If I would have had these videos my explanation could have been easier. The animation and graphics are unbelievable quality. The Part 1 is a good umbrella explanation of the chip design in general and CPUs in particular. I will call this the 10.000 feet view. The Part 2 is the 1 foot view directly into the processor architecture so some industry lingo and knowledge is required. I would have liked to have a 3.000 feet and a 100 feet view for popularizing chip design and CPU for people who do not have an electronics background. Intel has all the capabilities to do it so please consider it. In the times of Artificial Intelligence and Biotech advancements making more people understand where all started and how it humans can benefit from their merger should be a good topic to cover. Looking forward for new videos from you.

[@Nelthalin]

Thanks Boyd for these very clear video's i knew the basics but Part2 was very interesting and helped me to paint a clearer picture of what was going on. I would love to see more of these video's and even go more in depth!

[@FullBrainiac]

The content of this video was so clear that I saw myself working at an intel lab for a brief second in a near future. Thanks Boyd !!! Great Video

[@SaladinG14]

Awesome animations and analogies, altogether very easy to understand! I admit I'm heavily biased, but I think even a lay person with some passing interest would be able to understand a few of the important big-picture points.

[@aaronchung9838]

This is so good, it is easy for a newbie to understand. And it’s not boring for someone who’s already knows how a CPU works.

[@jamespriest7328]

Love this intel!!! Do more of it and yes let the world know about this. Ads maybe.

[@spithere4933]

This magic! many civilizations shook

[@twpayne]

This is absolutely brilliantly explained and presented, thank you.

[@mfc1190]

This is literally amazing. Great explanation and great work on building these technologies. Speculative execution was really cool for me to learn about

[@DeepFrydTurd]

This is entertaining :) I already have a CS Degree and work as a Network Forensics Analyst but I still find this entertaining better than watching some non sense videos. I like learning about the physics of the electrons or photons inside the CPU highway and logic gates and conducting test's of new architecture designs in a digital 3D simulator environment.

[@binhnq_tokyo_shorts_24]

It was truly remarkable. The best and most stunning lecture about CPU that I've ever seen.

[@Happiness-lp9fw]

24:30 Yes, it was very beautiful 😌

[@Validole]

Very well explained. The microcode decoding part was especially informative.

[@ttlim6752]

Thank you Intel for putting this up. I like it a lot!

[@AlexSchendel]

Honestly an incredible series! They seem to have found a perfect balance of details versus overview. It's not so high-level to seem common sense and it's not so in-the-weeds to seem impossible to understand. Also, the animation work is amazing. Great work all around.

[@KillerLettuce]

This was really cool. Any can get a part 3 that explains how this is all translated onto a physical processor? How do we take these concepts and functions and make them work in the physical world?

[@localcashmere]

Think of it in this way, trillions of electric signals go through a CPU, these electric signals are sometimes of low current, sometimes of high current. Low current is interpreted as 0, while High is interpreted as 1. Now we have all the characters that make up the language of computers. The CPU then uses Hardware languages like VHDL to operate these 0s and 1s. This is how Physical things do software work.

[@pstefanics]

Incrediby well produced and informative. One question: at 4:58, shouldn't the time to complete a stage be 0.2 (1/5th) billionths of a second if the CPU is running at 5GHz? It looks like 5 billionths of a second per stage would give a 200 MHz clock speed.

[@computerscience-hx7vn]

Incredible! the explanation and animation both!

[@mistercohaagen]

Haven't been this captivated since reading Peter Norton's pink shirt book; "Programmer's Guide to the IBM PC". Deep and geeky is what the future is made of.

[@Sakur.aiMusic]

This was actually extremely informative. I already knew a little bit about micro-architecture before hand. And now, seeing how some of this works, both the re-order buffer and branch prediction seem like they could be exploited to run unsigned code.

[@marcuspvxea]

7:00 at "Branch Prediction" is this what the cache memory does? storing the right paths and then when the branch appears again it know where to go?

[@julienp4563]

Thanks for this content, I liked it. I wish and hope more technical content like this one in the future.

[@aimanbryan1424]

This is beautiful.

[@renzomarini2480]

Please do more of these! I'm really enjoying the series.

[@mattanderson2074]

Absolutely brilliant. From start to finish.

[@thomasdevisser]

These videos are so impressive, I would pay for a full course

[@MrHav1k]

This is an incredible video!! Leave it to Intel to produce it. Thank you!

[@keshavmadhavan51]

@ 22:42, Isn't the value of V8 being modified by instruction 5? If yes, shouldn't instr 5 be queued before 4?

[@ljwobker]

This is really great stuff, but I found a bug in your code at the 5:00 mark... A 5 GHz processor doesn't mean "each completes in 5 billionths of a second" -- it means that each completes in 1/5 of a billionth of a second. It's a clock every 200 ps(thanks Ryan), not a clock every 5 µs... But at least we didn't divide by zero!

[@SaladinG14]

Nice catch!

[@RyanSchulz]

1 / (5 GHz) = 200 ps

[@Reinturtle]

It is a freaking miracle that we can make these things work reliably!

[@kentlisius7675]

I really liked the TV sticks with the embedded technology they came out with. Above all I've found that the key to unlocking the potential of any product is to have in specification RAM from a quality manufacturer!

[@slyblood85]

Awesome videos I can show people to help them understand what I am talking about, only thing I think was missed(unless i missed it) was how hyperthreading works in the pipeline.. that'd been cool to show.

[@vaidotasremeika7200]

Absolutely amazing, thank you!

[@AliceyBob]

I have not got words for congratulate this amazing videos !!!

[@sahandsalam4627]

Extremely motivative and well comprehensive.

[@amanrawat1458]

Please keep teaching us similar content. Some people like us are thirsty to learn

[@tosemusername]

Well done, Intel. Loved it. Wish there was more of this.

[@DANKAF]

very helpful for CS students

[@vladmihai306]

Great video, congrats for making it!

[@TalonsTech]

Good stuff. This was highly interesting watch. Enjoying my 11900K. Looking forward to Alder Lake and Intel’s GPU launch.

[@michaelpietarila3145]

This is by far the most informative video I’ve ever seen on the architecture of cpus I finally understand almost everything about how they work and why they behave the way they do simply incredible thank you so much

[@mallikarjunareddyankinapal5977]

Great summary of uArch. Awesome!

[@RohanKumar-wf9sc]

This was a great, short and in-depth explanation with awesome animations & examples. Please make more such videos.

[@johnsmith7256]

I think his analogy about the speculation is relatable to life. I fail over and over until I get what I wanted. Computers are spending more times failing then computing.

[@nadranaj]

great video with excellent graphical representation to simplify the complex concepts.

[@vanshthakur7060]

what a beautiful and educative illustration!

[@Arkan_Fadhila]

Thank you for this beautiful explanation of modern cpu. I hop you don't stop producing this series. I think GPU will be interesting topic to discuss as we all know intel have great iGPU today and hopefully will release discreate gpu soon

[@Anurag_Saxena]

superb. mind-blowing. beyond one's imgination!

[@dennysgrimaldi9623]

This is really good, nice video

[@pierreboyer9277]

It feels like uOps are the actual basic instruction set. Which makes it feels like ISA is actually a higher level language hardcoded in the hardware. But then what is the point of the higher complexity ISA and not using uOps as the basic instruction set directly? Is it why x86 has like 2500 instructions in its ISA? And RISC-V on the other hand as less instructions. 50 I think. Which sounds like many more than the really basic instructions so I guess they also use uOps?

[@storyls]

>Why not use uOPs as the basic instruction set directly? You could, but the issue is that it’s going to cost you a lot of memory. Really it’s just space complexity, instructions take up little memory, uOPs a lot. uOPs are basically a bunch of wires that go throughout the CPU and say things like “connect register 4 to the bus leading to the ALU” or “write output of ALU to the register file.” Each uOP also has to tell which modules of the CPU stay on and which stay off, and for the vast majority of instructions, each uOP is going to be sending a LOT of 0s to all the modules that don’t need to be operating for this instruction. While an instruction alone can take up say 2 bytes, each uOP could be telling hundreds of modules what to do. The decode stage itself is pretty dumb usually. It essentially uses storage, the instruction is an address and in that storage for that address there is some firmware for all the uOPs. Also each architecture can have all sorts of different uOPs for the same ISA.

[@mycollegeshirt]

Man if you guys could go even deeper, it whatever just amazing work

[@samfitness7198]

At 9:54 is there a way to make the comparison of the variable faster so it won't take long to tell if it's true or false? if I compare it to your analogy I mean to say that what if your aunt responds to your call quickly so you won't have to take the wrong direction in the first place! Would love to hear from you on this, Boyd.

[@justsomejazz]

Thanks so much. This is fantastic. I'm using this to teach my daughter.

[@michaelsandrik9819]

This is a great series! Hope there are more of them!

[@malleshkoujalagi1125]

Awesome!!! got clearly instruction-->decode-->uops and ooo execution, dependent uops execution. Please clarify how data caches are used if uops are memory bound?

[@OTechnology]

This is an incredible video!

[@nguyenkien5837]

Best video about CPU i have ever seen Wish you the best, INTEL

[@orelmac]

Loved it. Thanks!

[@dabay200]

was looking for a video like this that explains branch prediction just stumbled upon it - but I need more detail, never the less excellent explanation of CPU architecture

[@Van_Verder]

Stellar presentation!

[@pierreboyer9277]

Thanks for the video. I learned interesting things !

[@MrJackPL]

This is just awesome!

[@mycollegeshirt]

That was soo soo fantastic, I can't believe it wow.

[@egalanos]

Really well made and communicated and much better than I was expecting.

[@jaynorwood2]

compilers can currently unroll loops with constant loop counts, but could this more efficiently be handled by hard-coding instructions to a branch predictor?

[@storyls]

As in an instruction hinting to the cpu what branch to take? It’s possible. The Pentium 4 actually did support these branch hints, but it seems Intel has abandoned that since for whatever reason. I think it’s because modern hardware branch prediction has gotten good enough that it’s not needed anymore. Loop unrolling still benefits, even if you hint to a cpu to always take a branch, with a loop you are guaranteed to guess wrong at least once. Not having branches also allows the compiler to make other optimizations.

[@aleb34]

the pitch at 4:57 gave me shivers

[@hendrikwillemadrianusthart2233]

It's nice, would it be possible to split up the code and use multiple branches and a sort of cyclic redundancy check to reset other branches or even make these follow continuous in adaptation of new info of the proven right branch.

[@Validole]

Will you make more of these? They were incredibly informative: before, caches and pipelining were this black magic that was hard to reason about, especially as my previous reference point was essentially AVR MCU architecture (let's leave aside PIC because that's an entirely different beast altogether).

[@elhadjiousmanediallo1618]

Highly informative

[@Nour-eddineTaleb]

Very well done, but still waiting for the cache episode.

[@stachowi]

Totally found this by accident, but so informative.

[@mariocortes2670]

Great job and great video!

[@praveenalapati5234]

Excellent Presentation.

[@Olibelus]

This was amazing, thank you!

[@NizarElZarif]

The video is very well executed, but I think you went a little too fast on branch prediction stuff. I already know who it works but I had a hard time following that example, especially when talking about the assembly code. But this video is very well done.

[@karlstenator]

Such an awesome breakdown, thanks so kindly for posting! Great video!

[@sunilkumar-ls2yb]

great and simple explaination dude

[@shaxjl]

very very great video!! thank you very much!

[@friendlyfripptit2228]

This mini-series was excellent! yummy good!

[@JoseJimeniz]

If you want a more technical explanation, that in a lot of ways explains some of it much better, look up Eric Brumer's "Compiler Confidential" video. He goes into nitty-gritty detail the internal fetch-decode-pipeline.

[@Cardroid]

Can Mr. Phelps do another video or another series explaining X86, ARM and RisV architecture and why Intel is designing X86 when Apple is going with ARM in their Macs.. Thanks!

[@aleksandar5323]

I have a question: In Superscalar execution, when one uOps depends on another, as you are physically pushing the instructions down the pipeline, where do you store the results? is the separate stage going directly to the register, which is completely off the pipeline or how can I visualize this? Thanks for the great video, by the way :)

[@DamlaFatih0605]

It is not mentioned in the video but with Out of order execution you don't directly write or read registers but to Register Aliasing Table which holds a temporary copy of the registers this allows dependencies to be solved one by one.

[@pierreboyer9277]

Out of topic question: Why the silicon waffers has chips printed on the outter edge? Those can't be used as they are only parts of the chips so why bothering having them on the waffer at all?

[@Not_a_lier]

Why can't we have (small) cores that are dedicated to branch predictions. Is latency the problem or software compatibility?

[@anonymouscommentator]

Thank you very much for these kinds of videos, truly amazing.

[@paramveerteli]

Seen both parts. Great....

[@emilienamaury3839]

Cause this 2 videos, I want read more and more about this subject, so thk.

[@dynamic_pointer_cast]

I kind off missed why there are multiple fetch operations and multiple execute operations. I think that's what made branching so complicated. Would it be simpler if after fetching one instruction, you execute it abruptly before fetching another instruction?

[@yashas9974]

Processors kept continously improving their frequency for two decades until the 2000s. Further increase in frequency would become physically impossible or impractical (very high power consumption). The new concept was to focus on increasing instruction level parallelism (ILP) instead of vertical scaling up the frequency. The idea is to execute more instructions in parallel instead of executing them in-order one after another. A superscalar processor has multiple execution units as shown in the video. Such a processor can execute several uops at once. You want the backend to be saturated with sufficient operations to extract maximum performance. Therefore, you need to fetch and decode multiple instructions at once to have sufficient resivor of instructions to keep the backend busy. The more in-depth answer would be that you need lots and lots of instructions to be able to break dependencies and ensure better performance. Imagine a pair of instructions where the second instruction uses the result written in the first instruction. You cannot execute the second instruction until the first instruction finishes. You cannot ideally dispatch the second instruction immediately as the result of the first instruction is generally available towards the end of the pipeline and the second instruction may require it earlier. You will have to stall the pipeline (by inserting no-ops or bubbles that do nothing) for a few cycles to make sure that the result of the first instruction will be available to the second instruction when required. Every cycle a pipeline stage sits idelling is a waste of power and potential performance gain. Modern processors execute instructions out-of-order (not in the program order) so that you can execute some other independent instruction instead of the second instruction while you wait for the first instruction. The more instructions you have in your current set of fetched and decoded instructions (known as instruction window), the more easier it is to find independent instructions. This way by mixing instructions, you can minimize the number of cycles that wasted (if any at all!).