IR Drop & EM - English Version

This video contain IR Drop & EM in English for basic Electronics & VLSI engineers.as per my knowledge i shared the details in English.
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[@ramyajaithik3844]

This is the best channel your explanation is very good 👍

[@saicharan-xu1ub]

This is the Best Channel to learn Layout concepts Great initiative Sir

[@analoglayout]

thx u my friend

[@venkatasaikarthikvaranasi7303]

@@analoglayout Hi Suresh Kanna sir, yes. thank you from one and all once again.

[@AyashAshraf]

With due regards, i want to make a (some) correction(s) At about 15.50 in the video you said that with temperature the resistivity of metal decreses which is not the case. The resistivity of metals increases with trmperature. Additionally the EM is not due to heating of the metal, rather due to the dislocation of the ions by the higher current density than normal. Hope you will correct this. However it is a great initiative. I have learnt some important points from your videos

[@Keshav-rh4zw]

if temperature increses some electrons will start to occupy the conduction band and thus contribute to conduction, lowering the resistivity.Hope this conclude

[@AyashAshraf]

@@Keshav-rh4zw but that is the case for a semiconducting material. Here we are talking about metals which have a postive temperature coefficient meaning with temperature the resistance increases

[@ferozmohammad5689]

@@AyashAshraf I Agree. Metals have positive temperature coefficient of resistance. As the temp increases, the resistance offered by the metals increases.

[@lanxin7906]

Thank you Ayash! I was so confused when looking at the video I totally agree with you.

[@alfiyashaikh3754]

As temperature is increased resistivity increases because as we heat the atoms tend to move fast and collide each other with therefore increases resistance.

[@parkavikannan3704]

Each and every video is very useful sir.. Tq.. Best videos for learning bascis of layout.

[@analoglayout]

Thank u my friend

[@Abhishek_raj_Aaryan]

It may also happen due to the increase in current in metal, the heating effect of the material comes into the picture as H=i^2 RT. So due to the access heat, metal may gets damaged.

[@raviraju1450]

Thank you very much for your excellent explanation.. 👏👏👏

[@sivaranga3137]

Nice explanation

[@kesavaramsatyavarapu5202]

Your videos are too good Please... Take a session on double switching problem...

[@ramamurthy7937]

Thank you sir, please make more videos on Physical design concepts thank you

[@shubhamkumar-xl4ob]

very good video for analog layout basics

[@lanxin7906]

wait wait wait @15:58, why does everything else on google tell me that increased temperature means higher metal resistance? I mean that's why superconductors are kept at 0 K right?

[@analoglayout]

Each and Every metal have their own heat handling capacity , so based on the meterial property this will change

[@dearchinna]

Have u done metal stacking is it's really prevent IR&EM issues

[@analoglayout]

Ya ... This will help

[@LokeshrLoki]

Thank you sir

[@yuvakishore1350]

Nice videos sir Please explain about effects of electro migration and how it will effect

[@dasarinikhil14]

Apart from metal stacking/more metals can we use dummies ?

[@analoglayout]

No, adding dummies will not help to resolve EM/IR

[@dasarinikhil14]

@@analoglayout basically EM will create short/open circuit?

[@suresh.kannan]

Both are possible, but most of the case open ​@@dasarinikhil14

[@saivijayabhaskargade1528]

thanks a lot sir ....great explanation.

[@analoglayout]

thx

[@purvavatamwar9421]

Why do we need to consider IR drop for Vss rail because even if there is voltage drop in VSS the o/p vtg will be 0v. So why we consider vtg drop for vss ?

[@gajjelakondapavan9089]

if we increase the width of the metal, can we overcome IR problem...?

[@analoglayout]

ya we can reduce the resistance ...

[@PavanKumar-ii3gm]

If in schematic pmos one cell is there generated in layout one cell why we add concepts fingers multiplier unitcell so many cells why we generating sir

[@mohammedafzal534]

Good explanation! Explain more & more concepts related to vlsi layout.

[@bipulpal7719]

Nice video...hoping for more video for analog layout

[@analoglayout]

thx for your support , sure i will upload new videos

[@TrendyLifestyleTL]

For IR drop I think we can increases the width of metal if we have space is it correct ?

[@analoglayout]

Ye

[@vbag42]

@@analoglayout what?? how?? Rs is directly proportional to width

[@UDAYKUMAR-pe7np]

One thing to ask,how can you say that metal resistance will reduce by increasing i temp around 15:55 min . In metal resistance will increase by increasing temperature. In semiconductors resistance will reduce by increasing temp.

[@vikramyogan2501]

Sir one doubt, in the prevention of EM, you said that going for higher metal prevents EM but as you said earlier, higher metals have low resistivity. So how could this prevent EM?

[@analoglayout]

When a metal go to High temperature , it's resistance will increase , so we have to keep low resistance metal .... And also higher metal have more thickness ...

[@anilkumarpattapu7984]

@@analoglayout in video u said when temp increases resistance decrease

[@meerapadhy8213]

How EM will get reduce by increasing width of a metal ?

[@saravanakumara8080]

Bro, one doubt. Will parallel shape creation reduce signal IR?

[@analoglayout]

What if u add 2 resistors in parallel .....

[@praveendesunagi7315]

Sir could you please make a video on ESD ?

[@SAURABHSINGH-yd4lz]

Detailed explanation 👍👍

[@analoglayout]

thx for your support

[@pkb8517]

If IR and EM both happened simultaneously then which one will be fixed first

[@analoglayout]

EM has to fix first, so automatically IR will be fixed

[@pkb8517]

@@analoglayout but for fixing EM we have to increase width of metal then resistance will decrease and if resistance decrease then current will increase which fixed IR but if current increasing then how EM is fixing?

[@ravikadiyala8273]

Nice...

[@vivekvivekmondis5175]

While metal stacking, we need to follow the metal orientation

[@Kanna.suresh]

It's not possible

[@sireeshakosanam5522]

At what temperature EM occures

[@yuvakishore1350]

Hiiiii sir Please explain about metal open and shorts in electro migration

[@anilkumarkurra1314]

sir could you please help me how to do Monte carol analysis in cadence virtuoso

[@ravaligangula7589]

I want latchup topic please put on you tube these videos are helpfully so please put on

[@analoglayout]

il upload asap

[@ravaligangula7589]

Asap means

[@analoglayout]

sorry , im busy with projects , may be il try by this Sunday ...

[@ravaligangula7589]

I need this for interview

[@ravaligangula7589]

Monday interview so i want

[@asmisharma3163]

Too many ads in this video. In less than 10 minutes I skipped three video and they're still coming. The information is good but too many ads are distracting.

[@analoglayout]

It's a only revenue for me , so no other option .... Take KZbin prime membership for ads free video

[@asmisharma3163]

@@analoglayout Yes I can understand.

[@mandavaraviteja]

Thank you 😊

[@sampathkumarmatlapudi8250]

what is em rules? can you explain that

[@analoglayout]

EM rules can be differ from technology to technology , for exact EM Ruels details you have to refer DRM file

[@sampathkumarmatlapudi8250]

Analog Layout thank youuuu.. please upload all layout effects latch up, matching,sti.... etc

[@analoglayout]

sure bro , asap you that all videos will be available .... thx u for ur support

[@analoglayout]

ok sure

[@RohitVerma-qu6eu]

Now, cool. Actually I saw the same video above which was in tamil accent.

[@prabhatatha5543]

Wrong explanation that higher metals have high doping.......

[@analoglayout]

Could you share the detail reference?

[@nandithak1570]

nice explanation

[@bolakamadhu9222]

Thank you sir