Latch based clock gating technique and introduction to ICG

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking
Here's the link:
www.udemy.com/...
Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.
Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more.
I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.
So, hope you enjoy learning this course in the same way we enjoyed making them.
Happy Learning !!

[@paul2413]

Finally, a useful video on clock gating. Thank you so much!

[@paul2413]

You do speak quite fast though, I understood you fine as English is my native tongue but try to slow down for those whose English is not their first language

[@vamsikrishna-in9ps]

why this much of fast, any one is beating ?

[@coastalfly5508]

Nice video.. But could you please tell me how glitch occurs in enable?

[@purushothamv2623]

Very nice and clear information, but little bit faster. Excellent and thank you so much.

[@malesai3893]

Great video sir

[@vikasakinepally5656]

Thanks for the video. I have a doubt, if I have a glitch in EN at 1.5ns(a short pulse with 1.4ns to 1.6ns high) what will be my QL output and what will be my AND gate output. I may see a glitch at output of AND gate right?

[@hemantsaxena369]

what happen if the glitch on enable comes some where very near to transition from high to low.

[@155stw]

Great video! But thank God for yotube 0.75 speed multiplier.

[@zhichengwu7945]

yes, latch prevents the glitch happened due to EN toggles at the high portion of the CLK. but what if the EN got a glitch at the low portion of the CLK. It still need a synchronizer.

[@varunsharma3860]

I think if EN gets a glitch when CLK is LOW, latch will pass it through to QL but output of the cg1 AND gate should still be LOW as CLK is LOW. Correct me if I’m wrong.

[@santhoshrajolla7072]

not bad