Computer Architecture - Lecture 11a: Memory Controllers (ETH Zürich, Fall 2020)

[@tarekemad7899]

Thank you for this informative lecture , we are building a test bench for a HMC controller and this lecture adds a lot to me

[@chunlinyang-g6p]

Thanks for your dram controller share.

[@vasaviinduri7445]

Great and latest information. Thanks a lot Onur for your wonderful information.

[@aliuzel4211]

Thank you for your great info and effort.

[@mmkhans]

Excellent Information , Thanks

[@Dks-2224]

14:45 DRAM purposes 23:50 request = I want data from this addr -> which DRAM doesn't understand -> should be translated into commands by MC 28:10 read write 동시 불가. bus direction delay = read_write_latency | write_read_latency