Logic Family - III: NOT, NAND, and NOR Gates via NMOS, PMOS, CMOS by Dr. Alkesh Agrawal

This Lecture describes the design and working of NOT, NAND, and NOR gates by nMOS, pMOS, and cMOS. It also describes the classification of MOSFET as well as symbols and characteristics of n-channel, p-channel depletion and enhancement MOSFETS. The diagrams are made in MS Visio for better understanding of the concepts.
By Dr. Alkesh Agrawal