Mod 'N' Ripple Counter | Digital Electronics | Lecture 36

[@hardiksachdeva4920]

thank you sir for this amazing series ... aapne digital electronics ko kaafi easy krke samjhaya hai 👏👏

[@knowledgecampus07]

Thanks for your feedback. Do share with your friends to support us. Best of luck for your endeavours. ✌️

[@mr-ix2ze]

Sir in low high said that if pst is 0 then out would be one but you wrote 0 in the output

[@RijuPandey-pu4ne]

yaa exactly

[@ayandippaul3108]

Sir paheli bar jab aap active low ka table kiye uspe toh preset 0 hone se output 1 aayegaa!! Par aap ispe 0 kiu kiye?? Please mujhe samajh nahi aaya!!...

[@pratikdhagude2614]

Same question

[@arvindjindal1913]

you r right

[@ayandippaul3108]

@@arvindjindal1913 bro mera iss question puchne ke baad 2 semester ho gaya abhi bhi answer nahi aaya🙂💔😂

[@arvindjindal1913]

@@ayandippaul3108 😂😂😂

[@anayatali9914]

​@@ayandippaul3108 Abhi lagta hai 4 semester khair se ho gae hongy

[@Sau735]

woh bhai 1st table pey ek output 1 hona chaiye nah? jisme preset par 0 hai preset 1 banata hai na?

[@krishan6392]

You are right bro

[@socialsmileplatform1913]

Ha bhai galat btatya hai

[@kunalchaudhary2808]

Yes

[@devvikas2102]

Bhut accha bhai it is helpful in my exam time before 5 hours of exam

[@hgguys2605]

sir did you not cover Sychronous Counter in any lecture?

[@pankajkumar-lf3bl]

Very good explanation, but last wala glitch/ flash hoga seconds k liye because of NAND gate delay

[@iam-Coder]

6:27 sir the output will be 1 there

[@abhisheksahu305]

synchronous counter padhaiye sir pls

[@jai.shri.ram.3000]

am i right like here just to reverse the q0 and q1 to 0 we had used the nand gate over here the only possibility for the truth table for 1 and 1 to be zero could have nand gate

[@vaibhavbhatnagar3739]

synchronous counter k video bano na sir

[@erdeepak]

Sir clr clear hota hai aap clock padh rhe h... Confusion ho gaya

[@Abhishekbxr]

same problem

[@ganesh66866]

sir how can do mod 56 or big number

[@123amitsolanki]

Thank you so much sir

[@anshrathi3397]

one mistake when making the table of active low when preset low output is low which is wrong by mistake . i.e, 1 thank you

[@ashishrathore6860]

teach correct, dont do mistakes, it waste time

[@VijaySharma-ss4qd]

sahi kha bhai

[@goggledtech47]

J K flip flop never goes into dilemma state, S R flip flop goes into dilemma state. J K flip flop was designed to make J = K = 1 a valid state. Correct me If I am Wrong.

[@gamingchannel1456]

yes

[@socialsmileplatform1913]

Active low ka table

[@socialsmileplatform1913]

Bhai galat bnaya hai

[@satyabrataghosh6127]

😢 bohot bekar explanation