Modulus of the Counter & Counting up to Particular Value

[@MultiWiff]

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I couldn't get to understand counters up till now. Thank you very much. I keep studying from you videos.

[@BalaajRaza]

First of all thanks for creating this playlist. Like its been 9 years since its uploaded and till today it is helping so much students. I am preparing from your channel solely for my Digital Logic Design Exam. But I am confused a bit about the MOD condition. We used a NAND gate that generates output of 0 when the MOD = 0 occurs. But when the output of NAND goes in JK-FF it is inverted as seen in the diagram that it have a bubble. So instead of NAND we should use AND gate so we generate output of 1 and when it is sent to flip flop at clear it become zero and flip flop is cleared.

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[@manojguha2046]

Thank you very much .. Clear and precise explanation better than any book

[@kritikasingh585]

As per waveforms clock is sampling data just before the negedge, so it should read 5 (101) and then do clear instead of 6.

[@isuckatthisgame]

6:20 is all I needed. Thanks!

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[@hassanalshehri6855]

In this example, the requirement for the counter is to count up to 5 (101), however, the combinational circuit for the clear input allows the counter to count up to 6 (110). I'm thinking that the combinational circuit for the clear input should be (Q_A Q_B' Q_C)'. That is once the counter reaches 101, the counter should start counting from 000. Please let me know if i missed something. Thnaks!

[@hassanalshehri6855]

***** Oh, I see. Thank you for clarifying this to me.

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well explained sir..all my doubts are cleared after watching this video.

[@Chavan-zg8wb]

Another Approach towards such Q's I want a function which gives o/p as 0 for value >= 6. Other wise 1 for value

[@anthonysalim8672]

Thank you Neso Thank you very much . I should send the link to my professeur

[@dimension_rc]

Important: The nand gate should be designed on 101 ( at 5 as output) as we dont want 6 as output so it must be reset befor 6 is arrived i,e. at 5 as output we clear the flipflops. rest everything is correct 👍

[@Randsome1]

Then 5 won't show up in output, right?

[@SNEHAKANDPAL-ev3np]

​@@Randsome1but how would you get Qa,Qb,Qc corresponding to 101 for generating clear if the output corresponding to them isn't displayed?

[@isuckatthisgame]

​@@SNEHAKANDPAL-ev3np You clear your outputs when it reaches 110 (representing a decimal value of 6). It will be your output only for a short period of time. For example, if you are designing a counter up to 13, you want to reset it on 14. Because if you reset it on 13, you will lose that data.

[@SNEHAKANDPAL-ev3np]

@@isuckatthisgame Yes I got it. Thank you

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my prof should watch these lectures

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Simple n clear explanation.. inshallah I will score sooprgrade

[@himanshusingh1483]

brother first of all i want to thank you a lot for such a great and deep explanation of this topic. But i'm a little bit confused that when we were making a mod6 counter than why we reset our ckt on 6th clock cycle cause if 6th cycle applies then our ckt will definitely count till decimal 6(which we don't want) and then it will reset.

[@madhumantiray1041]

Clock starts counting from 0, so the 6th clock will count 5 and the 7th will again start from 0 (probably)

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Saying Thank U is not enough

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Sir in the description please upload the contents of the board as pdf so that we can use them as notes.

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Excellent teaching .

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really it was helpful for me during exam period.

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Thanks a lot sir....

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thanks sir,love from VIT VELLORE , TEACHER dhanabal

[@sohamsandipawate6386]

(9:56) when clear is 0 output is 0. But this is low active clear so shouldn't 1 be given to clear instead of 0???

[@KirkHammer-fj2of]

I disagree, i think we should trigger CLEAR when '5' appears , becoz Qc ,Qb, Qa, already show 101 before triggering CLR, , after '5' they trigger CLR and display '0'. Plz convince me how '6' is "Not displayed" when Qc ,Qb, Qa, = 110 after then they trigger CLR, , (in your ckt 12:30 onwards , i think '0' appears at 7th clk edge and 110 = 6 appears at 6th clk edge )

[@krishnasimhavemulapalli7124]

if we do what u have said...5th count state will be unstable...so when 6 came it is cleared..and 000 will come

[@sarthaksg]

6 will be the output(QcQbQa) for the time equal to the propagation delay of the combinational circuit. As soon as the combinational circuit detects 6(110) as input, the clear is set to 0. This clear will ASYNCHRONOUSLY (ie . clock independently without encountering the negative edge)update the outputs as 000(QcQbQa) and the counter will function as normal for next states. *Clear and Preset are asynchronous overriding inputs. .They don't depend on the clock edge.

[@kevinzhao7959]

@@sarthaksg thx

[@Manster-minds]

I too think that when 101 is countered immideately clear should be triggered

[@agstechnicalsupport]

Very instructive. Thank you !

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Thank you so much

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im not good in english but i understand you very well. niiice

[@shafqatjamal8766]

Very good explanation

[@kartheekmudi2480]

Tomorrow is my ece lab exam now I am learning this things😅

[@isuckatthisgame]

8:58, but from where are you getting those Qa, Qb and Qc? shouldn't it be connected to flip flop outputs?

[@HelloWorld40408]

Thank You Sir

[@023_debarghyadebnath3]

9:23 we can use a 2 ip nand gate with Qb and Qc as inputs, right??

[@gurveerkaur8154]

Concept cleared👍🏻 tysm !

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Sir u r like a god for us... Love u and gbu sir

[@ptt2102]

Great! Now I got it. Thank you so much.

[@vamshikrishnaradharapu6928]

Hii sir ... I am from Hyderabad... I have a doubt please clarify.. At 10:39 you connected logic 1 to preset so that no changes will happen. But at preset you have given a bubble then preset takes logic 0... In that case Then all Qa,Qb,Qc values will become 1,1,1 thent it is completely contradict to our question.

[@kartikbhanderi9210]

Here bubble means that it works as active low signal means whenever 0 is given as input it will set Qa...Qc to 1. ☺️

[@ankanbrahmachary6581]

bubble represents that the input should be active low and doesnot changes the input

[@prasangsinghal262]

Fabulous..... Can I use 2 input nand gate and set its input as Qc and Qb...??

[@ex0rrr]

Great videos! Just have a doubt that if this is a ripple counter why aren't we using Mode control input (MCI) as you taught in previous videos?

[@OfficialRajSingh]

Because this is a up counter.

[@AndrewKiethBoggs]

You use the Mode select signal when you have an up/down counter, to change between the modes. Here, he is only describing an up ripple counter. Ripple refers to the asynchronous clocking of the flip flops.

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keep posting such videos..!!!! very helpful...!!!!

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wow , works like charm , thanks

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saved my semester

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Very nice representation

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thank you

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thank u wo much neso academy

[@illuruvigneswarreddy9469]

I think we should design combinational circuit at 5(101) not at 6(110) Becoz, if we design combinational circuit at 6(110), Then we also must get 6 at the output...but we need to skip it as they asked for mod-6 counter not for mod-7 counter Pls correct me if iam wrong

[@gauravmandal007]

Thank you so much sir this is very helpful. 😭😭😭😁Thanks for saving me..... I m 12th std student.

[@aruneshroy8220]

please sir show one more example on this topic of modulus of counter

[@vikramdubey410]

easy to understand now...

[@AmitEngel]

What if I'd like to perform this way of counting: 0--> 3-->6-->2-->3-->5-->6? Will it be possible using the counting way u've shown us?

[@speakingwordsindia5631]

Please explain the generation of spikes or glitch

[@dzuyng5315]

- Modulus (số mod) số trạng thái của bộ đếm (đếm lên hay đếm xuống không quan trọng). - PRESET và CLEAR tích cực thấp (hoạt động khi tín hiệu ở mức thấp). Dùng để thiết kế bộ đếm với 1 giá trị MOD cụ thể: dùng thêm cổng NAND (input tương ứng với các bit của giá trị không thuộc MOD (MOD + 1), nếu là 0 thì thêm cổng đảo, nếu là 1 giữ nguyên), output của cổng NAND là 0 sẽ được nối với tất cả ngõ nhập CLEAR của các FF. PRESET = 0: Q = 1; CLEAR = 0: Q = 0 (không quan tâm đến CLK hay ngõ nhập J, K). - Khi vẽ giản đồ xung, khi tới giá trị MOD thì tất cả Q đẩy xuống 0.

[@ChanHungNgo-t1o]

VN ne