Modulus of the Counter & Counting up to Particular Value

Digital Electronics: Modulus of the Counter & Counting up to Particular Value
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[@MultiWiff]

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Sahi kaha

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Thank you so much❤, I have exam to write today and you made me understand what my lectural could not explain well..

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i just can't believe that its 7years old video and still one of the best!!!

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one request i want to do is, post videos on VHDL and memories as soon as possible.

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Amazing 😍. Indeed, you have explicated everything sir. May God bless you and increase the knowledge abundantly.

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I couldn't get to understand counters up till now. Thank you very much. I keep studying from you videos.

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[@mohammedsalah9838]

Thank you very much , the best in digital electronics

[@kritikasingh585]

As per waveforms clock is sampling data just before the negedge, so it should read 5 (101) and then do clear instead of 6.

[@zmh27]

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[@illuruvigneswarreddy9469]

I think we should design combinational circuit at 5(101) not at 6(110) Becoz, if we design combinational circuit at 6(110), Then we also must get 6 at the output...but we need to skip it as they asked for mod-6 counter not for mod-7 counter Pls correct me if iam wrong

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very clear and helpful. A big thanks from RV college of engineering student.

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[@atharvabais892]

Sir in the description please upload the contents of the board as pdf so that we can use them as notes.

[@himanshusingh1483]

brother first of all i want to thank you a lot for such a great and deep explanation of this topic. But i'm a little bit confused that when we were making a mod6 counter than why we reset our ckt on 6th clock cycle cause if 6th cycle applies then our ckt will definitely count till decimal 6(which we don't want) and then it will reset.

[@madhumantiray1041]

Clock starts counting from 0, so the 6th clock will count 5 and the 7th will again start from 0 (probably)

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[@ADNANAHMED-eo5xx]

Saying Thank U is not enough

[@dimension_rc]

Important: The nand gate should be designed on 101 ( at 5 as output) as we dont want 6 as output so it must be reset befor 6 is arrived i,e. at 5 as output we clear the flipflops. rest everything is correct 👍

[@Randsome1]

Then 5 won't show up in output, right?

[@SNEHAKANDPAL-ev3np]

​@@Randsome1but how would you get Qa,Qb,Qc corresponding to 101 for generating clear if the output corresponding to them isn't displayed?

[@isuckatthisgame]

​@@SNEHAKANDPAL-ev3np You clear your outputs when it reaches 110 (representing a decimal value of 6). It will be your output only for a short period of time. For example, if you are designing a counter up to 13, you want to reset it on 14. Because if you reset it on 13, you will lose that data.

[@SNEHAKANDPAL-ev3np]

@@isuckatthisgame Yes I got it. Thank you

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well explained sir..all my doubts are cleared after watching this video.

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Thank you so much for everything sir. We want gate EEE of all subjects sir please kindly do this for poor students sir 🥺🥺

[@hassanalshehri6855]

In this example, the requirement for the counter is to count up to 5 (101), however, the combinational circuit for the clear input allows the counter to count up to 6 (110). I'm thinking that the combinational circuit for the clear input should be (Q_A Q_B' Q_C)'. That is once the counter reaches 101, the counter should start counting from 000. Please let me know if i missed something. Thnaks!

[@hassanalshehri6855]

***** Oh, I see. Thank you for clarifying this to me.

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[@HelloWorld40408]

Thank You Sir

[@sujoyroy1658]

What if we have to start our count from a particular value say 2 (010)?

[@vijayaveluss9098]

Once the count reaches 111 Make a NAND gate that gives zero only when all of outputs are one. Use it to reset the first , preset the second and reset the third that way, it will be 2.

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[@abongfaith1683]

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[@khanjangajera8094]

Excellent teaching .

[@agstechnicalsupport]

Very instructive. Thank you !

[@AmitEngel]

What if I'd like to perform this way of counting: 0--> 3-->6-->2-->3-->5-->6? Will it be possible using the counting way u've shown us?

[@raakinsmummu5290]

Simple n clear explanation.. inshallah I will score sooprgrade

[@sohamsandipawate6386]

(9:56) when clear is 0 output is 0. But this is low active clear so shouldn't 1 be given to clear instead of 0???

[@shafqatjamal8766]

Very good explanation

[@faryzryz1482]

wow , works like charm , thanks

[@ex0rrr]

Great videos! Just have a doubt that if this is a ripple counter why aren't we using Mode control input (MCI) as you taught in previous videos?

[@OfficialRajSingh]

Because this is a up counter.

[@AndrewKiethBoggs]

You use the Mode select signal when you have an up/down counter, to change between the modes. Here, he is only describing an up ripple counter. Ripple refers to the asynchronous clocking of the flip flops.

[@user-bu8mg7uq3s]

thank you

[@prasangsinghal262]

Fabulous..... Can I use 2 input nand gate and set its input as Qc and Qb...??

[@vamshikrishnaradharapu6928]

Hii sir ... I am from Hyderabad... I have a doubt please clarify.. At 10:39 you connected logic 1 to preset so that no changes will happen. But at preset you have given a bubble then preset takes logic 0... In that case Then all Qa,Qb,Qc values will become 1,1,1 thent it is completely contradict to our question.

[@kartikbhanderi9210]

Here bubble means that it works as active low signal means whenever 0 is given as input it will set Qa...Qc to 1. ☺️

[@ankanbrahmachary6581]

bubble represents that the input should be active low and doesnot changes the input

[@ptt2102]

Great! Now I got it. Thank you so much.

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saved my semester

[@asadullahkhan3808]

assalam o alakum i just want to say you are the best teacher of this subject

[@isuckatthisgame]

8:58, but from where are you getting those Qa, Qb and Qc? shouldn't it be connected to flip flop outputs?

[@adityajaiswal4605]

really best digital electronics lecture for BTECH students in whole youtube

[@rachidguernouti3263]

can we use a decoder instead of the NAND gate to restart our counting

[@vikramdubey410]

easy to understand now...

[@giahinhnguyenle2826]

Great! If I want to build a counter that change states from 0 to 2 to 4 to 6 and to 8 in decimal, how can i do this? Should i build a ecitation table or something like that ?

[@anasasim3856]

Can you also please create a course, which teaches teachers how to teach? I will show it to my professor.

[@pranavrocker13]

how to design mod 5 up/down counter ??

[@exol_ruchan]

super helpful

[@yash7972]

very good lectures regards NIT KKR

[@KirkHammer-fj2of]

I disagree, i think we should trigger CLEAR when '5' appears , becoz Qc ,Qb, Qa, already show 101 before triggering CLR, , after '5' they trigger CLR and display '0'. Plz convince me how '6' is "Not displayed" when Qc ,Qb, Qa, = 110 after then they trigger CLR, , (in your ckt 12:30 onwards , i think '0' appears at 7th clk edge and 110 = 6 appears at 6th clk edge )

[@krishnasimhavemulapalli7124]

if we do what u have said...5th count state will be unstable...so when 6 came it is cleared..and 000 will come

[@sarthaksg]

6 will be the output(QcQbQa) for the time equal to the propagation delay of the combinational circuit. As soon as the combinational circuit detects 6(110) as input, the clear is set to 0. This clear will ASYNCHRONOUSLY (ie . clock independently without encountering the negative edge)update the outputs as 000(QcQbQa) and the counter will function as normal for next states. *Clear and Preset are asynchronous overriding inputs. .They don't depend on the clock edge.

[@kevinzhao7959]

@@sarthaksg thx

[@Manster-minds]

I too think that when 101 is countered immideately clear should be triggered

[@aleponzo4024]

So, the same clearing and presetting idea can be used for counting down to a particular value also?

[@balramsharma5887]

thank u wo much neso academy

[@heitlerremlalfaka4063]

sir, questn, does the NAND gate logic work for all counters that count to a specific value, in this case we caount to dec5 and after that it restarts from 0 and the NAND gate helps did that, what if we want to count to 7 and reset after that, will the NAND logic still work in that case?

[@adwaitambekar9615]

thanks sir,love from VIT VELLORE , TEACHER dhanabal

[@asmabader5758]

Thank you so much

[@arihantjain8347]

keep posting such videos..!!!! very helpful...!!!!

[@jaydeeppaul4239]

Sir, can we just solve the K-Map for MOD 6 counter?? Then combinational logic will become NAND of Qb and Qc..

[@gurveerkaur8154]

Concept cleared👍🏻 tysm !

[@minjinsin8797]

the waveform is wrong

[@apostolosmavropoulos177]

dear sir please explain, if we dont have negative logic for PST & CLR (so the PST=1 -> Q=1 & CLR =1 -> Q=0) inputs, are we supposed to use nor gate instead of nand fore reset condition?

[@heitlerremlalfaka4063]

also sir, i have simulated the ckt on www.falstad.com/circuit/e-counter.html i think instead of NAND for teh reset the op of NAND should be OR again with 0 then given to all RESETs.. then only teh ckt will work as desired. correct me if i am wrong. Bcoz, the circuit above will produce RESET=1 => Q=0 FROM THE FORST CLOCK signal itself

[@Dr.SahadevRoy]

Very nice representation