VLSI :mealy sequence detector verilog code and test bench for 1010 and verilog programming

[@pradeeppurushothamanvadakk7360]

There are 2 types of sequence detectors, overlapping and non-overlapping. Here, it is overlapping type. If incase you are looking for a typed code, check this comment: module seq1010(clk, rst, in, out); input clk,rst,in; output reg out; parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; reg [1:0] c_state, n_state; always @(posedge clk or posedge rst) begin if(rst) begin out

[@VLSI-learnings]

Combination circuts you used not blocking statements it's not correct.. please use blocking statments

[@pradeeppurushothamanvadakk7360]

​@@VLSI-learnings Thanks for correcting. made the change. Yet to simulate and check the result.

[@aswiniv6428]

amazing sir, very clear explanation

[@VLSI-learnings]

Thank you

[@amitavishwanath5722]

Please do more videos on verilog hdl your videos are really good

[@VLSI-learnings]

Ok

[@gouthamrathod5056]

Do more example bro,,it is helping us lot

[@VLSI-learnings]

Ok

[@aswiniv6428]

i have exam tmr, this video helped me

[@VLSI-learnings]

Thank you

[@anime_thrones_endgame]

👍👍😍

[@umavathimarichetty2050]

Very nice explanation sir..can you tell how to drive data in both clock positive and negative edge

[@changeyourperspective1291]

very useful, nicely explained

[@VLSI-learnings]

Thank you

[@hemanthnalajala6751]

This is for overlapping case in sequential detector right ?

[@VLSI-learnings]

Yes

[@nalajalahemanth1144]

@@VLSI-learnings Thank you

[@biswarupdas2891]

suppose I'm taking input sequence 10101101010111110001010 Then what should I do in case of test bench writing? I'm mean If I follow your process the testbench will be lengthy, then please teach us another way to write testbench in such case.

[@AakashKumar-qq1ie]

use for loop he explained at the end of video.

[@hatsuki23.11]

i dont understand about "out = 1'b0" 4 turn

[@ranadeepgoud0015]

write verilog code for the bidirectional buffer and verify using testbench

[@maheshgoud3317]

Bro..! You missed the output instantiation in testbench code i.e., output as wire

[@VLSI-learnings]

Ok let see

[@hyat12]

Nice 👍

[@VLSI-learnings]

Thank you

[@VLSI-learnings]

Thank you

[@mohansardar5247]

showing Syntax error near "out=1'b0" while simulating on Xilinx ISE software.please help to solve this.

[@VLSI-learnings]

Please check syntax errors in the code... it may be some typo mistakesin code.. you have correct it...

[@mohansardar5247]

@@VLSI-learnings ok sir

[@catchyflicks]

@@mohansardar5247 I got similar error. Then I have updated the code with output reg out. It is working now.

[@mukulsharma8616]

Can we make a sequence detector without using fsm

[@VLSI-learnings]

you have to connect the sequence detector input "in" to 4 serial flops and and take extra four bit input to your design (what sequence you have to detect, give to "1010" to four bit input signal ) and compare with serial flops output with four bit input signal (what you added extra to your design) . you will get the result

[@ehtashamnaeem639]

will u plz send me the verilog code of sequence detector 0110 using jk flip flop.

[@ehtashamnaeem639]

i have state diagram and cir cuit diagram but i donnot know how to write the verilog of it.

[@VLSI-learnings]

Why you required this... real time we will use d flop not jk flop

[@geethkuldeep6113]

Telugu ga bro?

[@VLSI-learnings]

yes

[@emintuzcu6701]

please dont take your records at airport's plane taking of areas. thanks for information

[@VLSI-learnings]

Ok