Boolean Algebra And LUTs in FPGA

[@parasjain1048]

If you're only looking for LUTs just start from 18:00 xD

[@yakirkaye4358]

Paras Jain thank you sir!

[@zhaoyue9559]

Thank you! Really

[@tompol5433]

thank you good sir

[@Angadkumar_]

thanks

[@unkrishnendhu]

Thank you

[@Lwyte17]

Just ordered a Go Board, can't wait to start learning this stuff. Thanks a million man, people like you that share knowledge and make it easy to learn make this world a better place.

[@toufiqmusah6480]

It’s been 7 months. How’s the journey so far?

[@entrepreneurcoder]

For the FPGA example (A' + B' + C'), you could use De Morgan's theorem to rewrite it as (A*B*C)', meaning output 0 when you have 1-1-1, and output 1 for all other cases

[@brasildocara]

¡¡¡¡ PLEASE FOLKS LET'S FUNDRAISE TO BUY HIM AN ERASER !!!!!

[@adambynes]

LOL

[@blabla9800]

Why????, he already has got one!!!. Let him do things his way!!!!! If something works for you it does not mean that the same thing works well for others.:)))))))))))))))

[@DJFixNYC]

or some shirts

[@sonetmollick4630]

Please, you should not be mean. He is doing great!

[@russellokamura2022]

Thank you for these videos. FPGA resources are hard to come by sometimes and between the KZbin videos on your channel and the references on the nandland website, I feel like they have really helped me with my FPGA development. I'm here because I was watching some of your recent videos (mainly the interview question one) and realized how I lack a real fundamental understanding of the things going on under the hood of an FPGA. Anyway, thanks again, I'll be watching. Also, great name haha (had to say it).

[@jeremigendron3120]

Finally now understand how "wiring" works in an FPGA. I thought for the longest time it was controlling tension between gates (on actual physical wires). Now I understand that each LUT will "cache" which gates to apply to its inputs and yield an output (hence programmable gate array).

[@Aemilindore]

your series on getting started with FPGA's is just great!!!!

[@MsSaTify]

Nandland great still to this day. Someone get this guy a whiteboard eraser tho

[@Nandland]

patreon.com/nandland :)

[@chrisbeebe4326]

Just getting into FPGAs and this is fantastic so far. I look forward to the rest of your videos!

[@РоманТравкин-й2к]

Thumb up for explaining what are LUTs.

[@Sakura-kc4ms]

thank you for your good explanation we need more videos from you

[@JetNmyFuture]

I may send you a dry eraser ;) Hope there are more on the way.

[@brasildocara]

10:46 HAHAHAHAHAHAH !!!! two hours after he realizes there is not the 0-0-0

[@yasard1345]

You make really informative videos. Could you please arrange your videos in a proper sequence? Would be really helpful.

[@oluwatoniodetayo3141]

How do you know which logic gets precedence? Is it always "and" or is it the first logic operation from the left?

[@JoshDan12]

In class the other day, my prof was also talking about something called SLUTs. Can you make a video explaining what SLUTs are?

[@Nandland]

Not googling that one...

[@SkGow]

Thank you. That was helpful. Keep it going

[@wondermh406]

Thanks , Its nice that you explained from root.

[@Fnolepenoll]

Can you replace the two OR-gates(7:17) with a three input OR-gate?

[@brasildocara]

+cile88 +nandland I have the same question!! Exists 3 inputs Or--Gates ?

[@mikail5682]

great explanations, thank you

[@leahthegeek9677]

thank you so much sir you explain amazingly

[@petteral94]

Thank you for making these informative videos :)

[@justicehunt7136]

Very well explained 👍

[@MegaShivaji007]

keep the good work up

[@alexandrevenito1215]

Nice work! Congrats!

[@emmanuelbabu2215]

thank you for the videos!

[@terencewright2223]

Very good. Thank you

[@AhmedNegm123]

amazing work 👍👍

[@rishitpallav5470]

Does the precedence always follow from left to right? Or depends upon the operator? 14:03

[@aramgaribyan6248]

Your first FPGA is technically incorrect. You're supposed to use a 3-input OR-gate. The way you have it doesn't allow the 0-0-0 situation. :)

[@marbrydav9698]

Very helpful, thanks!

[@JacklapottTv]

18:00 LMAO, the guy lied to us, trust no more xD

[@almuhanadahmedsaidalhashmi4696]

if you want to understand start the video from the end and backword

[@Richardhu1983]

thank you. very helpful.

[@aerohk]

Thank you sir!!

[@josesoto7475]

Good work !

[@lunapresentsstuff]

Hi I have a question. How many LUTs do I need when I want to realize an AND Gate with 8 inputs ? Maybe two LUTs with 4 inputs ? How can I combine LUTs ?

[@Nandland]

The synthesis tools will take care of this. In the real world you don't often need to count individual LUTs.

[@lunapresentsstuff]

​@@Nandland What would a synthesis tool do, for example ?

[@ycthakor1984]

nice explanation dear

[@tombouie]

Thks

[@gurkiransb]

Cool work! Keep it up! :)

[@jitesh3005]

Thanks man...u r great

[@mohammedk.h.f3016]

Thank you

[@jigishparikh1968]

It does not explain what inside a LUT allows itself to reconfigure depending on the truth table you want to implement. Can you explain that?

[@bwack]

Hi LUTs are close to multiplexers. Look up the Shannon Expansion theorem. I can recommend googling "Implementation of Boolean Functions through Multiplexers with the Help of Shannon Expansion Theorem" . You'll find your answer in the conclusion of that document i think. The doc is not the best on explaining the theorem itself, for that there is a nice video on youtube. Can't remember the name of the video right now. I'm learning about FPGAs myself right now, are you ? :) Maybe you ask more what mechanism makes it reconfigure ? SRAM cells usually.

[@saptarshidas488]

I guess, a LUTs are a complex arrangement of logic gates (maybe NAND gates), in a matrix shape, where each of these gates are interconnected by wires. When we program a LUT, we actually decide which interconnections to activate between the required logic gates. That's how the LUTs can reconfigure themselves according to the boolean function. This is just my thinking, I don't know if it's correct.

[@raneelpawar7959]

Useful

[@DevaDeva-oq3kv]

Don't we have 3 input or gate?

[@campbell1175]

Not C sounds a bit iffy depending on how you say it really!

[@dalvi_]

Thank you ~ a CS noob on the way.

[@susanneschmitz9390]

Thanks for your Videos! I hope they help me to rock my Bachelorthesis :-) You're cool, clever and hot!

[@olivialinden8699]

Great

[@mandlik1996]

are you the russell from bully?

[@kumbaya234]

I have never seen a professor /teacher who wipes out the board with what he or she is wearing !! Are u still in business ? I like to get some help from you- paid services - I feel sorry for your T-Shirt !

[@masbro1901]

but you're not explain details about LUT, what is inside LUT, is it a hardware? is it a software? is it just line of codes? is it a memory? you just draw a box's name LUT. but thanks! well enough explained about other thing.

[@saptarshidas488]

I guess it is good to imagine LUTs as mini FPGAs themselves. A matrix arrangement of universal gates, interconnected by thousands of wires. Thus, several combinations of logic gate connections are possible.

[@user-cl7iu3ff3i]

القوية يمسح بأيده قحط مساحات 😂😂

[@imho2278]

8.50...000. C must have value of 0.

[@imho2278]

At 10.14 c is high and you called it not.

[@imho2278]

Your truth table will have no output for a not, b not, c not.

[@nenani1817]

Anyone else thinks this was really weird?

[@PrashantKumarSharma]

You liar 17:35

[@jeffreymelanson9230]

You should post a link to your videos on FPGAs.