Snooping-based Cache Coherency Protocol

[@c2838]

Clear and great! Really help me a lot! Thans for sharing this video!

[@rajeshprajapati1851]

Really, Cool Presentation.

[@chenyu8553]

Nice presentation! May I know what write strategy does Intel and AMD use? Write invalid or Write update?

[@Alexander-zt9kz]

Modern CPUs, Intel or AMD, use write back as it is faster than constantly having to interact with the MMU to write the change into RAM

[@MrSambitrath]

All modern processors use Write-back

[@niranjanchip]

Very clear and nice explanation. Thanks a lot!

[@prathameshkodgire8642]

welcome niranjan chip

[@florianmanuelschmid489]

great explanations!

[@stevechen7918]

One point seems questionable. Why p1 is in initial, cache read miss, it send one snoop read to peer. But no peers have this address, it read the data from main memory. Then put it status to share? Does it should be in Exclusive is better?

[@王祥-l3l]

At 3'31'', what will happen if p1 and p3 set the cache line at the same time?

[@jigsawcc]

I have the same question here= =

[@anglee8123]

i think it is similar to WAW (write after write) problem in the cache.

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