Introduction to JK flip flop

[@chrism7574]

Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.

[@last_time_I_pooped_was]

Now what are you doing in ur life?

[@chrism7574]

@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD. As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.

[@pav4540]

@@last_time_I_pooped_was i was wondering this too

[@aadvaitture]

how in the world did you not learn about flip flop circuits

[@yousufzohair4342]

Pretty Dumb I guess

[@alphasatari]

After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions. Things get really confusing when we moved to the J-K flip flop. Let’s start from beginning, We’ve two data storing elements i.e. 1: SR NOR Latch 2: SR NAND Latch They work the same but their truth tables are completely opposite to each other. i.e. SR NOR Latch truth table S R Q 0 0 Memory state 1 0 1 0 1 0 1 1 Not used SR NAND Latch truth table S R Q 0 0 Not used 1 0 0 0 1 1 1 1 Memory state After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop. Let me ask you a question. Can’t we use any other combination of gates? Of course, we can. See the possible combinations which will work as an SR flip flop. 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) You must be thinking what about the other combinations? 5. NAND-NOR 6. OR-NOR 7. AND-NAND 8. NOR-NAND These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits are not storing data we can’t use these combinations. The only possible combinations which will work as an SR flip flop are: 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) Hope, it cleared your doubt till now. But as we move to J-K and T flip flop. We again have some limitations. We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate Using this type of arrangement of feedback. Only two possible combinations will work i.e. 1. NOR-NOR 2. NAND-NAND Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop. If you want to use the remaining combinations for J-K and T flip flop 1. AND NOR 2. OR NAND Then, these two combinations can also be used if we make some changes in the feedback arrangement. Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration, “If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.” I tried every possible combination and their truth table. Everything in this video is correct and accurate. Hope it helped you!

[@gytisdramblewolfskis8521]

your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme IE in SR latch with nand if you give top input s and bottom input r while top output is q then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q' though there are other combination where the table would be correct as well IE nR->nQ nS->Q and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.

[@ghazikhan2624]

Wow great..... excellent understanding

[@shristisingh2417]

😨

[@RAHULTMNT100]

thanx saved me a lot of time

[@ir2001]

Bhai logic gates ki sale lagi thi kya

[@andrewwatts1997]

I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!

[@gowtham5168]

I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.

[@priya09213]

I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching

[@muniaferdoushi2168]

because he calls latches flipflops

[@303vasudevjha3]

There are teacher of our college who didn't explain

[@akhiljithk7173]

@Prateek Patel okay. I'll watch .

[@ChesswithPramit]

Dislike are from those teachers who were expelled for not teaching well...

[@SAM-yy3db]

KZbin removed dislike are you happy now ?

[@sneakyboii732]

for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊

[@rileshkhatri1209]

At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs

[@himanshkumarsahu6473]

yes same doubt..

[@rajaramyadav7546]

that is sr filp flop with NAND gate and that is correct. you are talking about sr latch with nor gate.

[@mooketsiruangngwako6204]

Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤

[@NaveenKumar-rv7fx]

Hi NESO, If Q is given back to J NAND gate Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻‍♂️

[@ava43518]

Sir you are a legend. I hope you get very successful in your life!

[@shayanshakil8922]

u r simply amazing! i hope you get all the success u deserve

[@sonusambharwal8828]

Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......

[@debanjanghosal618]

1:00 Why does the logic diagram represents a SR flip-flop with NAND gate but the truth table is of a NOR gate SR flip-flop?

[@bluebs899]

exactly. confused me too.

[@fahadbinislam588]

i also got confused but now figured it. The TT is for SR-FF : for this remember that SR FF consists of a SR Latch. Here the inputs are S,R for the FF, but the inputs of the embedded SR Latch are S* , R*. So if you consider the TT with the inputs as S*, R* then the Qn+1 values satisfies the SR NAND latch TT.

[@Clickershit]

Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz

[@s.prabin]

Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕

[@OswaldChisala]

That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!

[@TheGazanews]

+Oswald Chisala this is really confusing me how can we use NAND based rs F-F while using NOR based f-f ??

[@Clickershit]

Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz

[@ayanakash9900]

First time i understood toggling. You are legendary man🙏

[@hisetip]

Man, you are awesome. I'm studying for my test and you are the only guy that I understand! thank you so much for helping me. I'll drop my PayPal contribution on your website tomorrow. keep the great work!

[@adityababurajan9684]

explained....the whole concept in a very simple manner,..... thank u sir.....

[@vishalbharadwaj4896]

Your lectures are very helpful.

[@madhurkant7976]

Congratulations 👏👏🎊 sir for 1million subscribers , keep growing

[@RamanKumar-bl7dp]

Uyyyy7w

[@keshavraj5451]

00:06 JK flip-flop provides an advantage over SR and D flip-flops. 00:51 Introduction to JK flip-flop 01:42 The JK flip-flop has two outputs Q and Q complement. 02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case. 04:06 Analyzing the values for Q and Q complement 05:03 NAND SR latch can produce different outputs based on input changes 06:01 The JK flip-flop races between 0 and 1 06:58 JK flip flop output is the complement of the previous state.

[@NoName-li4jo]

EE101

[@OmarEmam-y3s]

thank you :3

[@onepiecebarca]

"you have already studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop" YES EXACTLY WHAT I'M THINKING, WHYYYY

[@tanusreenath2023]

Thnku so much for making this things so easy for us☺ u were a life saver to me😊

[@pranavshukla2009]

PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions. Your lectures are great. Thank you so much for them.

[@yannrezk5735]

he wouldve done them if you weren't screaming at him. thanks a lot.

[@tharunreddy5201]

Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..

[@OmarEmam-y3s]

type sht

[@andonrobert3911]

In 5:13 you said that the when input is 0, 1 from clock and 1 from K, then nand output is 1 but it should be zero, right!? And gate for three inputs 0 1 1 the output should be 1 and the compliment of it should be zero, correct me if I am wrong!

[@andonrobert3911]

OK got it, And gate means all input true then Output is true!

[@rajputnasir5617]

Thankuuuuuu sir You really help us alot. Clear concepts in a seconds. You really make difficult subjects easy.

[@hawak5652]

thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources

[@aneetakushwaha9058]

Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.

[@rudranarayanbaral]

Thank you so much sir. You are simply marvelous.

[@omenechris4698]

Great Explanation, one in a million! Thank you very much!

[@prathamgoel3386]

@5:27 can someone help me out here As S=0 R=1 and using SR Latch output must be ie Q=0 but here sir is writing 1 How ?? Kindly help ASAP 🙏

[@beatx2173]

Same

[@musicgirl_14]

Thanks again and again sir for your work

[@enlightenededucators]

I understood the concept well thank you so much sir👍

[@amandeep9345]

5:20 you say when input of sr ff is 0 and 1 the output is 1 and 0. but it's wrong. according to the table when input is 0 and 1 output is 0 and 1 only. o.O help

[@emanehab510]

i noticed that too .... but its right for nand sr output

[@tanzimtheunstable4239]

NAND gate 😑

[@jayeshlokhande6367]

kunal choudhary yes dude i got you

[@leongaraimarwendo8153]

he is correct, notice he said "SR LATCH" not "SR ff",

[@jayeshlokhande6367]

Aman Deep we have to use truth table of latch and not flip flop

[@haricharan9280]

Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir

[@Saptarshi.Sarkar]

Just discovered these lectures. Now I don't have to worry about my CC V

[@scott430tube]

Wow, your presentation was really helpful! Thanks :)

[@daremon124]

Great explaination sir I was totally understanded thank you for sharing this sir♥️👌

[@Hari-lg3fi]

Is it confusing only for me? :(

[@Mindrelifer191]

Yes

[@MasterXoergOwnsen]

If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).

[@NaveenKumar-rv7fx]

U are correct

[@Clickershit]

Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz

[@jayantrathore2789]

In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it

[@davidstern1699]

at 5:21 both nand gates in the second set are recieving 01 so both their outputs should be 1, no?

[@sahilsharma8237]

David Stern well ur doubt is correct but actually the mistake u r doing is that u r taking both the feedback values simultaneously dont do it simultaneously first take one feedback at a time and let the value of the one output change then take that changed new value as the feedback value for the other nand gate.You will get the correct answer.but here also start from the upper flip flop and not from the lower flip flop take the feedback that upper flip flop is getting get the new output and then take it as a feedback to lower flipflop. the reason for this is that nomatter how similar two flip flops are they always has some speed difference in them which is of the order of picoseconds so we have assumed here by taking q=0 and !q=1 that the upper flip flop is faster so it will get the feedback first.....hope ur doubt is cleared now

[@bhuvaneshwaranm7290]

sir ,i have been hearing your voice by this tutorial ,i just i want to see your face ,your tutorials are really awesome

[@bhuvaneshwaranm7290]

see you are crossing in my way

[@bhuvaneshwaranm7290]

did i do anything to u

[@bhuvaneshwaranm7290]

i just like that video whats wrong with that . You said "gay" that was really annoyed me

[@bhuvaneshwaranm7290]

so sry if i hurt You.plz dont cross my way.

[@studentcommenter5858]

He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.

[@biswanath6020]

Me referring this video in 2024 where there are n no.of videos I find this video as best as it only req information great job neso academy

[@taibatalat8766]

Explaination method is excellent

[@gorlabhanuprakash]

Sir when the CLK is low the circuit will get off by having the previous outputs in memory but why get J* and K* as 1.. At 2:40 in the video

[@MantharAli-l6x]

Great explaination and unorthodox English ❤😅

[@ManognaKothapally]

Thank u sir a very good explanation

[@stefanpuzic9785]

+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed

[@renusharma2963]

U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0. Hope this help

[@SaraJSurer]

i have learned so much things from you thank youu you are the best

[@vipingautam9852]

Thanks sir, All your lectures are well explained. Thanks :)

[@ronnieahabwomugisha5283]

THANKS A LOT, ITS JUST GOT ME READY.

[@ahmadjaradat3011]

Man, you are awesome.

[@EngineeringEducation]

Excellent video!

[@Official-tk3nc]

Sweet voice sir😁

[@Deepakfly]

I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....

[@Anurag_Dhrejen]

you took j=0 k=1 as similar to sr flipflop can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..

[@karamkassem9821]

Exactlyyyyy ! i need to understand that

[@moreefn]

Thank you sir🥺❤️

[@ssdubey6642]

thanks sir. that's so better explained as compared to others

[@aashitgarodia]

NESCO ACADEMY THERE IS A MISTAKE AT 3:00 when the case is j=1,k=0 you just assumed j=S and k=R saying that the truth table is same for JK and SR , you didn't derive JK truth table and proved it is same.

[@nishantsingh931]

sir how can we assume ourr self the value of Q (4:20)

[@rg1346]

the value of Q will depend on the previous state before input becomes 1,1 . so the Q value doesnt matter, it could be 0 or 1 but the working will be same

[@Fighter_Believer_Achiever]

Thank you very much sir🥳🥳🥳🥳

[@haru-ic8fe]

I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool

[@igorbecker2323]

In 3:15 I don't get why the TT for JK and SR FFs are the same. E.g. if J=1 and K=0, the output of the K-NAND equals 1 because K=0, but what would prevent the output of J-NAND from also being 1 and the latch being in memory state if neg(Q) was 0 previously ?

[@adityasaini932]

For all those saying the truth table is wrong, its NOT. The truth tables of NOR SR Latch and NAND SR Flip flop are almost similar.

[@marouanebicher5959]

hello there . i do have a very simple questions at 5:30 you said when we have 0 and 1 in SR latch the result actually is that Q =0 and not to 1 based on the table you have on your presentation any answer would be helpful .

[@munirahmoorman3602]

marouane bicher you have to refer to basic SR Latch table . When Reset = 1, Qnot=0

[@naveenchiluveri8495]

@@munirahmoorman3602 thanks bro Iam too wasted my time there

[@ayabarakat8998]

Is there a difference between a JK flipflop formed from an SR(using nor gates) and other SR(using NAND)?

[@OmarEmam-y3s]

yes

[@aatibmd991]

I m watching almost every 6 months

[@curiosityzero2151]

It was really helpful I apperciate your work!!!!

[@HaydenHatTrick]

are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop? Madness! PS, actually very helpful. Thankyou :)

[@sarathchandraprasadveluri1574]

why u are taking inputs at s=1 r=1 and latch at 2:45 sec and saying it as memory state??

[@manikanta9160]

nice videos sir....i am completely understand ....one more thing is there is some MISTAKES while u r explaining....plz correct it

[@professorbuffet]

So what do the JK, D, SR and T flip flops do in general? Do they control the amount of duty cycles in a wave, change the waveform, etc... ? I am still a little confused.

[@maxbreaker]

Have you figured it out because I'm also confused

[@professorbuffet]

@@maxbreaker which part are you confused on? I might be able to help

[@10_yogeshchandrapandey90]

Don't you think so, that clk. Must be edge triggered (as per diagram) ?

[@Moon_lovee]

His way of teaching makes me feel like... It's an offline class. Mean face to face.

[@fitrihanifa9504]

isnt that a truth table for SR in a NOR?

[@folorunshonurudeen2564]

Can u recommend textbook on digital electronica

[@myrtopieridou9911]

amazing job man! keep going !thanks for the help! I think you are the reason for my success !!!!!

[@kmonish9119]

you guys are great. iam able to understand about flip flops. good job. all the best guys and thank you : )

[@humedomer6652]

Thank you sir for clarification toggle state

[@唐德轩]

good clear explaination,thank you

[@kushagraagrawal1739]

Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too

[@akashsingha2616]

simple to understand videos!

J and K inputs should be swapped. When J goes high, we should see Q output high, and in your video it is opposite (wrong)

[@relaxingmusicandmeditation516]

It is so helpful sir.Thank u

[@masbro1901]

but your explanation is under "assume" n 4:16 , but what is the reality ? and the result Qn+1for (clk, S, R) (1,1,1) is Qn' , if they are racing why Qn' ?? and how become toggle ? as in "assume" condition ?? assume is not real right ??

[@ivahp]

@mas bro Because no matter what assume at the beginning for Q and Q(not), the result is always a toggle - a change of state. Therefore, you will have constant switch b/n 0 and 1. It's all about change of the state.

[@rameshbandaru7523]

but if we assume like that then what is the need of jk flip flop.what if we have assumed same thing in SR flip flop

[@ignatiusnwankwo5134]

Hi, thanks for the video. I have a question. Why is the truth table for an SR NOR gate flip flop when the SR flip flop in the diagram is a NAND type? Thank you.

[@debanjanghosal618]

Exactly. I was confused as well. Can someone explain?

[@WARnationLD]

Very good videos

[@freud6343]

awesome videos..helped a lot..thank you

[@mirandoo300]

no comments you are the best

[@nubrbygaming736]

What is the flip-flop definition

[@1712sagar]

sir I think there is a mistake. during the second round you have 1 at the input of upper right nand gate and 0 through Qbar. so the output should be 1and not 0. please explain. thank you

[@Biju_Saha]

Yes . The guy messed up there .

[@littleprincess250]

in sr flipflop s=1, r=1 when i remove the clock the circuit fluctuates y does it happen

[@yousufzohair4342]

Because of the toggle state.. It keeps toggling 0 to 1 and 1 to 0

[@AsamNivedha]

5:20 when we gave inputs s=0 and R= 1 for the SR NAND latch the answer should be Q=0 and Q' = 1 but why is Q=1 and Q' =0

[@Mat_thias]

It is a NAND SR flipflop which is an active low input, hence the apparent inversion.

[@mohdkashif9830]

becoz thats actually s* and r* that we give to the latch

[@Clickershit]

Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz

[@adityajaiswal4605]

salute to neso academy very good explanation

[@MeenatchiSundaramM]

sir while write output for inputs your not condidering q and q' inpus just writing outputs considerin only j and k and enable or clock

[@picturization3914]

In the last case where clk=J=k=1, why do we assume Q=0 and Q'=1? In the very first instance, shouldn't both Q & Q' are zero when we try to get to the State Q1?

[@iancoleman6352]

Isn't the truth table you have for the SRFF for the nor gate implementation?

[@tanzimtheunstable4239]

this was grately helpful. I had a hard time understanding toggling