Lec81 - Demo: Vivado ILA and VIO on hardware

[@letstalkscience6494]

Thank you for this amazing tutorial on ILA and VIO...so easy to follow and reproduce. Looking forward to more quality content like this!!

[@mbuaesenju8514]

Thank you I had a cool demo with the Nexys 4 board

[@blr543]

Good one we need more such videos from iit .......👍

[@Dom-bo8wd]

Hi! Thanks so much for the video! Very clear and helpful :)

[@fmm5322]

Hi. Tell me how to use the ila in non project mode. Means i have grouped some probes on ILA in project mode and i want that these grouping remains interact in non project mode

[@jafarabbas3728]

Sir what if our design has around 100 I/O pins ,how can we map them onto the FPGA?

[@shri1527]

how much BRAM/memory is being used specifically by ILA ? how to check that? I observed value of counter to be shown on ILA is from 0th to 1024th ....what if we want to increase the lenght to be observed on ILA

[@harissajwani2583]

You can check it from Vivado tool. After synthzing your design with ILA, click on report utilization, and you'll see resources used by each component of your design.

[@vishnupriyakota5849]

Sir did you connect the fpga board to PC while running VIO and ILA...can I do this without a board with me??

[@nandithaec]

You can do all steps till generate bitstream without the FPGA. But, you cannot observe any outputs without programming it on the FPGA. So, you need the FPGA to observe the final outputs

[@vishnupriyakota5849]

@@nandithaecok thank you for your help

[@coobypop5532]

@@nandithaec @I am not able to replicate this project as its showing (make sure the clock connected to the debug hub (dbg_hub) core is a free-running clock and is active.) If I directly connect the input clock ,then it runs, also am using zybo board. please let me know.

[@coobypop5532]

it was showing a clock freerun issue. i was able to fix it..just remove the reset at clock wizard and it works

[@diwakarm6354]

Please make a video for RGMII interface using IP cores