OSVVM in a NutShell, VHDL’s #1 Verification Methodology (Jim Lewis)

OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both simple unit/RTL tests and complex, full-chip or system-level FPGA and ASIC tests. OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives. With OSVVM and a good team lead, any VHDL engineer can do verification - and have fun doing it. OSVVM grew rapidly during the COVID years, giving us better capability, better data structures, better test reporting (HTML and Junit), and scripting that is simple to use (and works with most VHDL simulators). This presentation will show how these advances fit into the overall OSVVM Methodology.