Co-simulation with Renode DPI and SystemC interfaces (Piotr Zierhoffer)

The Renode simulation framework is being used in a number of projects and open source initiatives developing new ASIC-targeted IPs and SoCs. It lets you mix fast, functional full-system simulation with co-simulated RTL blocks. This talk will show how Renode's DPI interface support allows interfacing SystemVerilog IP simulated with Verilator or other DPI-capable simulators via a range of bus interfaces as well as present the newly-added SystemC TLM support. Renode's co-simulation capabilities together with features like trace-based modeling as well as flexible support of the RISC-V ISA including simple definition of custom instructions, help explore architectural choices, analyze the security and performance of in-development SoCs, develop software pre-silicon, and build rigorous, deterministic test suites which guide teams through the entire development lifecycle of SoCs.
Presented on Sept 13, 2024 at ORConf. Learn more about ORConf at fossi-foundati....