Maybe the audio can be fixed next time.

Interesting tool! Lots of questions regarding cocotb-bus yet this tool seems different in that it expects the user to define the drivers and monitors etc. Do you intend to provide common bus functionalities within Forastero in the future? @peterbirch3717

It is not exponential, Mr Venn.

Goldner Shores

I see a slide on stack machines - and no mention of FORTH?

Skipped a bit through the document and it misses an important bit. In Europe VHDL is dominant but the open source community clings very strongly to Verilog. We have some good OSS VHDL simulators like GHDL and NVC but they are simulators and not synthesisers (I know there exists a plugin for ghdl and yosys). As long yosys doesn't ship first-class VHDL support, there will be a huge obstacle for students and engineers in Europe. Similar situation is also with SystemVerilog, the support in the OSS tools is lagging behind. To add to this, there is also no good support for OSS mixed-language simulation and synthesis. Once you have VHDL and SystemVerilog properly supported the entry barrier for thousands of students and engineers is lowered.

So What are the key advantages over cocotb-bus?

That guy is insane🧨

0:02 Matt Venn - CMOS inverter speed run 3:20 Nathan Gifford - Zine Lightning Talk 6:59 Frans Skarman - Ethernet in 3 minutes (?) using Spade 10:13 Todd Strader - Verilator and rr 12:47 Marek Pikuła - CI setup for multi-platform software project 15:41 Christiaan Baaij - Clash in 3 minutes 19:09 Simon Cook - RISC-V and OpenRISC Compiler Feedback 21:57 Francisco Izquierdo - Side channels for hardware design 25:00 Peter Birch - Define Your Data Structures in Python 27:18 Christophe Alexandre - Artificial Netlist Generator 29:27 Oron Port - Lessons learned from 3 student case studies exploring 6 different HDLs 32:37 Piotr Węgrzyn - Coreblocks 35:52 Olof Kindgren - IP-EXACT...ly where I want 37:50 Stefan Wallentowitz, Julius Baxter - Thanks to the sponsors, local organizer and everyone 39:37 Rob Taylor - Amaranth SoC, VS Code extension, ChipFlow

Smith Gary Perez James White Jeffrey

kzbin.info/www/bejne/oHulhmOAZ8iYg68 🙂

YYYIIIIISSSSSSSSSSSSSSSSSSSSSS !!!!

Congrats Ajeetha

To the person asking about Real Number Modeling: see the cocotb docs under "Tutorials > More Examples > Mixed-signal (analog/digital)" and "... > System Modeling".

01:14 Audio starts, assuming a known issue

Audio does not have enough quality!

Somebody please give the guy a glass of water, so he does not have to smack all the time.

The problem with this approach is that students will not want to study in the courses that teach using tools they will not be using in the industry. The commercial tools are very cheap for academic users and open-source tools will not gain acceptance unless they are used in the industry. Unfortunately, I don't see anyone from Industry in this working group.

Amazing, thanks for bringing this topic to the light and discussing on it!

Possible to re-upload without the picture flashing? Thanks

One of the best accelerate NIC hardware on FPGA presentation I've heard for free

Where can I get a Sonata board?

Can SystemRDl support SystemC Verifcatoin Constraint from the SCV package? And then generate the SystemC header file including the constraint where the registers are described as Struct or Classes?

Boss, Your videos are very good, but please rename them with correct order.

Wonderful stuff!

your research is important to keep us not being enslaved remember we need a open source standard to have a new monetary system that's not controlled by the world Elites

I trying to find Renode Emu Tutorial

This is so cool. I had actually read that very paper on wave pipelining, but didn't consider it practical (for all the reasons you cite). That fact you pulled it off and on an FPGA to boot, is impressive. Re. the audience comment: self timed logic is interesting too, but is completely different; wave pipelining is overhead-free, where as self-timed logic has buffers for each "wave". The main difference from synchronous is that the clock is effectively local to each stage (which has its own pros and cons).

Really a nice presentation. But the demo seems not work through the command provided.

This looks a lot like Cadence ADE Assembler. It seems like I'm going to have to take some time and do some analog/mixed-signal design with the open tools!

Great presentation by the tickler!

Are the slides from this presentation available anywhere?

The UVVM forum seems to be quite silent and deserted. If the UVVM is being used so much, where do people post all the questions?

Is there any detailed comparison between UVVM, OSVVM and VUnit anywhere?

This is very cool! I have two questions: - Can it be ported to a PCB design with off-the-shelf components with reasonable price? - Can the memory/update algorithm part be handled on a PC's CPU/GPU then communicated to the board via USB? (to reduce board complexity)

This is amazing what Tim has developed. CACE makes life of analog designers much easier to validate their designs and build confidence before tapeout.

Availability of IHP rf pdk in open-source ecosystem will be a big boost. Looking forward eagerly to using it for some RF stuff.

Wow this is super useful!

xkcd 927

Looks useful!

Epic

First

🎉🎉🎉🎉🎉 YEAH!!!!!!!!!!!!!!!!!!!!

Bravo! 🎉

Thanks for having me, @FOSSiFoundation!

That whole conference was very informative and great fun! Thanks to all those who came and to FOSSi Foundation for setting it up and also giving those who couldn't be there the opportunity to see the talks, too, with these videos. I hope to have some more cool stuff on the analog stuff in the near future and hopefully something interesting for you next year :)

This sounds interesting! wanna give it a try

Nice work!

So this is for folks who doesn’t know SV?