PCI Express IOs Basics

[@iliangardevski7129]

Maybe the problem is that, when gate transition occur transistors P2 and N1 are both turned on at the same time. Same thing happens with P1 and N2. One way to solve that problem is to separate gates and add latency between turn off and turn on gate signals. Firstly the on state transistor have to become 100% off after that off state transistor can be turned on. I hope that will help.

[@santoshgurral66]

Hi.. why is that +/-350mv signal has an dc offset (as you mention it as common mode voltage) where is this common mode voltage coming from..can you plz explain this

[@alok20001]

Very Nice

[@alannobakht8503]

PCI Express is not a Bus, PCI is.

[@MagnumCarta]

PCI Express is a bus. It is a more modern version of legacy PCI. Most PCI devices these days use PCIe rather than legacy PCI.

[@chosesomething]

If I'm not wrong, it looks like a bus to the software but in reality it is a Point to Point (P2P) communication. It looks like a bus to s/w due to the presence of switches and bridges connected to root complex (RC)

[@CD-dm7sf]

@@chosesomething I agree, I think of it that way. At teh PHY layer its a point to point dual simplex links (4-wire) but to the SW that's abstracted out - note that the device drivers/SW that were were written for the classic PCI/PCI-X (parallel buses) will, generally work transparently on PCIe

[@varunhajela9498]

pcie works on CML logic not on LVDS , your understanding is incorrect

[@Vishrut.Dave94]

He tries to implement LVDS using CML... He knows what he is doing... His understanding is just fine

[@jagadishk4513]

Buddy, u need to fact check before critiqueing someone.

[@duttabikash0013]

Bad explanation. No supporting explanations for whatever circuits drawn. Would be better if you would have put the reference links of your studies.