PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design

[@shubhrajyoti3150]

Best video in sanity checks!

[@radheshyamshaw8672]

PnR and CTS has not done yet then how can we check timing (Clk)related issues

[@VLSIAcademyhub]

When clock is not built then it's better to check setup issues mostly.

[@ramojiraobheemavarapu5545]

what is the importance of multiple clk ips

[@sumanth8878]

Can we force Input transition and output capacitance on all the ip and op cells? , because they are the values used to find cell delay in .lib and each cell will have different cell delay

[@slakshmivasantha]

Already there will be values of cell delays in .lib .Then is it ok that no error is raised if values are not matching as in .lib?

[@Siva-rz2xj]

could you please give an examples to unconstrained endpoints

[@Azzubhai047]

THEY DONT HAVE ANY OUTPUT.they have only unconstrainned startpoints only

[@ashokkumarm2488]

before floorplan any sanity checks is needed

[@VLSIAcademyhub]

Before floorplan there can be sanity check like functional verification if synthesis is done

[@Azzubhai047]

CORRECTNESS OF INPUTS LIKE .LIB,LEF.V ETC

[@praveen5490]

Hi, what is the difference between set_load and set_ouput_delay ?

[@ashokkumarm2488]

output delay it is assumed value of external delay used for interfacing the value where as the load value is from lib