Quartus 18.1 Install (Windows 10) and Gate-level Simulation

[@mantonlab9255]

To get gate-level simulation to work, make sure the test bench module is in a file of its own.

[@muhammadfaheem3869]

I want to know, Does it work accurately? If I can install only Quartus 18.1 lite without updates

[@mantonlab9255]

There should be no difference in accuracy between different versions. Note recent FPGAs are not supported though for gate-level simulation because they have moved to on-chip debugging.

[@electronicseverywhere204]

When I am trying to install the Qartus then there are showing ' you don't have Quartus software installed in c: \intellFpga you need to have Quartus prime software installed in the directory

[@mantonlab9255]

First install Quartus lite, and only then, install the update to it. (It sounds like you are trying to install the update first.)

[@pradeeptirukkovalluri852]

Sir I tried in the same way as you did using Quartus 18.1. But during gate level simulation I faced following error. # ** Error: timing_8l_1000mv_100c_v_slow.sdo_typ.csd: syntax error, unexpected $end, expecting '(' # ** Error: (vsim-SDF-3445) Failed to parse SDF file "timing_8l_1000mv_100c_v_slow.sdo". # Time: 0 ps Iteration: 0 Instance: /test File: F:/Projects_quartus/timing/test.v # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./timing_run_msim_gate_verilog.do PAUSED at line 12

[@berllancman2377]

thanks