Resonance in RLC Circuits || Analog VLSI Mastery (Cohort 0-10)

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[@user-dn7ep3gg8y]

Sir, how did you obtain Vmax/ root(3) for -3db level for parallel RLC after applying log? This differs from series RLC's 1/root(2) multiplier?

[@HimanshuAgarwal_]

Written by mistake

[@HardikJain_YT]

Finally done with your challenging analog series , interview series and this rc rl series. My review is you teach very well and actually analyse things nicely ; I now have great intuition for RC ckts ; best wishes for this channel and my TI interview :) Thankyou

[@-MohammedShoiabMalik]

When will cohort 11-100 will come? Waiting for it please give update about it

[@nitinchinmay260]

How did you infer that the areas cut by x and y in 36:09 are equal? Is that equal everytime?? And at 38:24 WL = 10^3-10^6/2 is not very low. Infact it's very high(considering the magnitude of the frequency) Can you please comment on this sir?

[@HimanshuAgarwal_]

1) Graph will be symmetric about Wo. 2) You can't take magnitude there.

[@SumitGupta-om4zn]

Sir when cohort 11-100 will come please update as soon as possible 🙏🙏☺️☺️

[@user-nl7og4sd3y]

is RL or RLC circuit necessary for gate aspirants in ECE

[@HimanshuAgarwal_]

Yes, it is