Sir big fan from pilaniya academy 😂

Bhaiyya, Is it worth taking B. Tech in Electronics engineering(vlsi design and technology) in a tier 3 college?

Bhaiyya, Is it worth taking B. Tech in Electronics engineering(vlsi design and technology) in a tier 3/ tier 4 college?

This is because he analysed every test afterwards, cleared the basic and made fundamentals strong! Congrats bro, I learn a lot from gate toppers

Why would PMOS be off in 4-5v?

Which test series is best?

kzbin.info/www/bejne/nYOVYZiNo6-imq8si=P-KPXQ8v-dg9sw_n please solve this question sir

Handsoff ❤

Handsoff ❤

Sir in the digital vlsi Roadmap for physical design please explain sir..!

Konsa attempt tha?

Hi sir I wish to study for gate exam and i don't know what could be my step to be plz suggest me the idea and books and steps to do

Thankyou bhaiya, for this inspirational video!

Bhaiya off campus google hardware aur intel kaise apply krte vo dono nahi aa rhe campus mai intern ke liye

bhayya at 46:19 in the band filter diagram( omega c)l and (omega c)h should be interchanged right??

Sir, what will happen when I will turn 40. Will Vlsi industry fire me due to age or would i be able to sustain in industry? Sir isn't vlsi industry saturated ? Latest chip size is 2nm and will there be still jobs after 15-20 years ?

Where did you got this test series?

15:27 The transfer function will be 1/(sRC + 2) sir

Finally done with your challenging analog series , interview series and this rc rl series. My review is you teach very well and actually analyse things nicely ; I now have great intuition for RC ckts ; best wishes for this channel and my TI interview :) Thankyou

how can you guarantee that i1-i2 > i2 please reply thanks better maybe since vc2 is rising and its slope is decreasing so ir2 is decreasing same for ir1 since vc1 is rising (in last ques)

20:35 ir2 has to go down easily because ir2 charges vc2 and ir2 = c2dvc2/dt and over time dvc2/dt is decreasing so ir2 decreasing also ir2 is decreasing throughout since vc2 is rising throughout with decreasing slope

41:30 but if pole location is not same then response is not same and since initial conditions are same and both are of the form ae^-bt + ce^-dt + e ; so they can't reach the steady state at the same time rt ? Please reply Though by contradiction I agree both reach ss together but seems difficult to see using these equations ...

17:20 now I got the reason for considering C1 and C2 in parallel nice !

Gate vs jee which is harder?

TI ke apti ke ques ka lvl kitna hota hai @HimanshuAgarwal_

1:04:00 maza aaya !

Hello sir can we connect on LinkedIn. I want to know about something related to this field. I am also an final year electronic student...

Bro please upload that video which you have uploaded before Gate preparation from KZbin for financial issues candidates

Sir i didn't find roadmap for analog vlsi profile video

Cause Q2 ka op amp pos fdbk mai hai

Kafi trick kar rahe ho bhai ; dhyan hi nahi jata ki neecha n * gm hai ; nice nice

Assume D1 off D2 on then V0=0 limiting current through input resistor is 1/R so if Vin < -1 then this isnt possible if Vin < -1 then D2 must be off and D1 must provide the surplus current reqd in the input branch. I think it does not make much sense to calculate boundary condition by switching off both the diodes cause it never happens

Vin/2 ko Vin' manlo

For the alpha value it is -AR1 only if Rf is high enough to ignore loading , otherwise it is -A * (R1 || Rf)

Bro if u don't mind please tell me which app did u used for mock tests please tell me

Can you please provide the link of that video of how to prepare for GATE from KZbin... I saw that video yesterday and also I downloaded it... But today it is not avaible.. Plz help

You teach very well ; but I would like to point out Rout 1 > Rout 2 ; for bjt output impedance for very high emitter resistance is limited to Beta * r0 but for mos Rout 1 = gmro * Br0 ; for bjt Rout does not depend on gm. Clearly Rout1 is higher by a factor of gmro.

24:29 C is also increased so speed increases surely only when it drives a higher order load cap of some pF let say

3k + 75/2 hoga

This is extremely clever something which is not obvious at all ; i knew abt averaging but by one op amp nice

thank you sir,pls explain in English language foe further video's

hai sir pls explain english help full to all

whats your day to day responsibilities at your job?

slew rate ki vibe aa rahi

Can do Vi - V0(first part) = V0 (second part)