Roadmap for Open Source EDA in Europe (Stefan Wallentowitz)

[@danielgiesbrecht9701]

I appreciate the content but the audio quality of this recording was unfortunately quite poor: the speaker’s voice went from barely audible to clipping often.

[@OrangeEpsilon]

Skipped a bit through the document and it misses an important bit. In Europe VHDL is dominant but the open source community clings very strongly to Verilog. We have some good OSS VHDL simulators like GHDL and NVC but they are simulators and not synthesisers (I know there exists a plugin for ghdl and yosys). As long yosys doesn't ship first-class VHDL support, there will be a huge obstacle for students and engineers in Europe. Similar situation is also with SystemVerilog, the support in the OSS tools is lagging behind. To add to this, there is also no good support for OSS mixed-language simulation and synthesis. Once you have VHDL and SystemVerilog properly supported the entry barrier for thousands of students and engineers is lowered.

[@FOSSiFoundation]

Thanks a lot. This topic indeed came up in the workshop we had later that weekend, so far we had only covered simulation. It is in the TODO list for the next update, thanks!

[@RevolutionEDA]

The problem with this approach is that students will not want to study in the courses that teach using tools they will not be using in the industry. The commercial tools are very cheap for academic users and open-source tools will not gain acceptance unless they are used in the industry. Unfortunately, I don't see anyone from Industry in this working group.