PCB Layout & Decoupling - Understanding Impedance (Part 2)

[@kayitbilgileri]

Hi, there! Thank you for great videos. Thank you for your good intentions to educate people with your best. I think there is a mistake in the video where you name the Xc as Capacitor impedance and Xl as Inductor impedance. Xc is capacitive reactance (reactance in ohms) and Xl is inductive reactance (reactance in ohms). Reactance (symbol X) is a measure of the opposition of capacitance and inductance to current. Total Reactance, X = Xl - Xc (Where in your formulation it is not also very correct : You wrote it as Xc-Xl). Impedance (symbol Z) = The square root of (The resistance squared + Total Reactance(X) (difference of the capacitive reactance and the inductive reactance) squared). Impedance is a measure of the overall opposition of a circuit to current, in other words: how much the circuit impedes the flow of charge.

[@RobertFeranec]

Thank you. Yes they are swapped. I have seen it somewhere in the other comments and I thought I pinned it. Thank you for pointing this out again.

[@優さん-n7m]

@@RobertFeranec I am really trying to find out why would someone put in ferrite beads into PDN. I mean we want to minimize inductance right? I know that ferrite bead filters high frequency noise but am not sure how people decide which value of ferrite bead to use and also, where to use them and where not to use them and also, what is the difference between them and inductors.

[@jlysiak]

What I really really appreciate in You is that you are not afraid of standing in front of the public as a professional motherboard designer say: Oh dear! It is basically school knowledge, just oscillator but I learnt a lot! Yeah! These are facts that school teaches us but nobody is perfect and it is ok to say "I didn't know". Thanks a lot for sharing all your videos, as I'm growing up along with you! :)

[@RobertFeranec]

Thank you very much Jacek for nice words.

[@amirsaeed9163]

OMG! I remember those calculations from university but I didn't know that they are this much important in PCB design! You are officially my hero right now. not because of only this video, because of time and effort you put to do these for us. Thank you very much.

[@RobertFeranec]

Thank you very much Amir

[@AdamFJH]

No need to apologise for the slow pace of the series. You are doing a fantastic job explaining. This video has been very educational.

[@RobertFeranec]

Thank you very much Adam

[@Andrew-dp5kf]

A lot of electronic design (schematic and layout) is a balance of compromises, BOM cost, layout, tracking, emc, esd. As you say though, continuous improvement is what we all strive for. This is why videos like this, and communities like electronics stack exchange are super helpful, especially with PCB layout as this just doesn’t get “taught” you usually have to watch over the shoulder of the other engineers. A colleague of min always used to say look at other people’s PCBs Robert’s server layout videos were very interesting in that respect.

[@RobertFeranec]

Thank you very much Andrew

[@jerrymueckl3081]

From this video I was able to visually see what resonance is, and how one can use the intersection of the capacitive and inductive impedance curves to predict it. I appreciate the way you described engineering principles I thought I had learned long ago.

[@andredevilliers0]

Thank you very much Robert for your interesting discussion. I also understood that the impedance of a real inductor will increase with frequency up to a point. Once the frequency exceeds the inductor's resonant frequency, the inductor magically becomes a capacitor. This is due to the interwinding capacitance. The lower impedance of these interwinding capacitors start to short out the windings. PCB design is really black magic - more answers generate more questions. I always feel the more I know, the less I know. Another factor that complicates things even further is VCC (Voltage Coefficient of Capacitance). VCC is a phenomenon in Class II and Class III MLCCs where the capacitance will decrease under applied DC voltages. This effect is most noticeable when operating at voltages close to the rated voltage and where high capacitance is a critical parameter in the design. VCC occurs in all Class II and Class III -X7R, X5R, Y5V, Z5U, etc. So when you think you are placing a 1uF 1206, you might only get 470nF or even less. Maybe you can consider doing a video about it as well. Thank you for sharing your knowledge on the art of pcb design. I have learnt a lot from you. Regards from South Africa. Andre

[@aero91most]

Please, keep doing this, because I see that this topic mainly covers all important electronic subjects in my electronics university degree, but also applied to a real PCB, so I hope future students will find these videos :D Thank you!

[@RobertFeranec]

Thank you Miguel

[@merdogan-ee-engineer]

Thanks Mr Feranec. Looking forward to seeing part 3.

[@RobertFeranec]

Thank yo Mustafa

[@EDGARDOUX1701]

Excellent lesson Robert as always! Learned so much with the 2 parts. Hope there is a part 3, 4, 5, etc Regards from Buenos Aires, Argentina.

[@guillep2k]

Saludos, también desde Bs.As.!

[@RobertFeranec]

Thank you very much Edgar

[@yuriipiadyk1544]

Totally agree. Finally, someone has explained to me the impedance properly. I mean with intuitive understanding of what is going on in the circuit instead of just deriving the formula and saying okay, here it is, be happy) Looking forward to the next video!

[@yuriipiadyk1544]

@@RobertFeranec great idea of using simulations as illustrations to explain the theory 👍

[@RobertFeranec]

@@yuriipiadyk1544 Thank you :)

[@giannisasp1208]

Thank you Robert for this video series ! Very important information for everyone !

[@RobertFeranec]

thank you very much giannis asp

[@neuralnetwork653]

Thank you for the video, Robert. Please do not forget to mention in part 3 that there are plenty of techniques of how all this mess might be improved. For example: - Reducing the size of a capacitor will also reduce its parasitic inductance (that is why it is hard to see electrolitic, 1206 or 0805 decoupling capacitors on high frequency boards, 0402 and 0201 are the vast majority there). - Situation with tracks impedance might be improved by using multilayer boards (reducing the distance between the track and the ground plane). The 1.6 mm thickness board you showed is obviously not suitable for high speed layout. And so on, I am sure you know all these tricks.

[@RobertFeranec]

Thank you PS: I hope to cover these, just need to wait until Eric will have more time for our next call.

[@nelsonalmeida4694]

We need part 3 to unveil how to make our circuits better! I was looking for this knowhow with many friends and they always say: it's difficult to explain!!! And to prepare us to the next develops circuits over the megahertz... Thanks a lot for this valuable content!

[@RobertFeranec]

Thank you Nelson PS: I will try to cover it .. just waiting untill Eric will have more time for our next call.

[@WaveIO]

Hello Robert! great video! One small addition to it: @ 2:22 you can see that at point 3. the module of complex impedance "Z" is SQRT[R^2 + (XL-Xc)^2] which is true since the capacitive reactance will get lower with higher frequencies but on your video, later, @ 10:16 for example, the XL and XC have switched places inside the square root. You cannot subtract XL since XL=omega*L and it will get higher as the decoupling frequencies will get higher!

[@RobertFeranec]

WOW! The result will be the same (as it is square), but you are right, the equation at point 3 really is different from the equation what they show in the Part 2 ( 22:09 ) which I used in the spreadsheet. I didn't noticed that. Good catch! Thank you for pointing this out. I am learning something new every day.

[@IGobzter]

As a 1. year EE student, thank you! This is a great primer and will make me follow theory much more closely. You never know what you might miss.

[@RobertFeranec]

Thank you Huwite

[@patricko.5277]

Hello Robert! I really love this kind of videos. Please keep going!

[@RobertFeranec]

Thank you very much Patrick

[@DiegoColl44]

This video series is great ... !! I save them to my "favorites" videos to watch later. Today I could see the series and it was worth every second. Thank you very much Robert.

[@georgekariuki8614]

Great stuff Robert! I went from an amateur who knew absolutely nothing about electronics to making a prototype PCB in four weeks just by watching your content. Keep up the good job🤜🤛

[@RobertFeranec]

Thank you George for watching. I am very happy you found the videos useful.

[@jorditribo94]

Wow.... The video started with the definition of impedance and escalated quickly! I love it! Keep up with the good work.

[@RobertFeranec]

Thank you very much Jordi

[@mdchethan]

Great work Robert. I Can't wait for part 3 wherein I hope we get to see some suggestions and with some examples to fix the PDN impedance issue.

[@RobertFeranec]

Thank you Chethan

[@rjordans]

Thanks for taking the effort in making this series! I've had some trouble in the past with an RF amplifier that was oscillating due to bad decoupling and I found myself simulating things again. Just playing around with Qucs now and some estimates on the parasitics so not getting very close to the right frequencies but it does indeed show a nasty peak in the power delivery network impedance there.

[@oktemee]

Dear Robert, As always great video. Thank you very much for your effort and time. Being able to base the practical knowledge to the theory was excellent for explaining why we do stuff so, not the other way. I hope that you continue this series, would really like to watch the rest of the story. And of course many other topics. Kind Regards,

[@RobertFeranec]

Thank you very much Kerem

[@zhitailiu3876]

Thanks Robert! Really great enlightenment! (I would like to see the the remaining talks with Eric, which was paused in part 1.) It is because the very first simulation (uploaded in 8/13), I started feeling that there is an LC tank between power source and IC's power pads. At that time, I haven't understood why high PDN impedance causes higher current density accordingly. Now everything is clear now: Current ( or energy) simply flows back and forth between capacitors and parasitic inductors, NOT into the power pins. Except for frequency changes, load condition is still the same. It simply acts like an excitation of LC resonator circuit as we study step responses. Great series of videos!

[@dominikliberda4017]

I'd like to see the rest of the call with Eric too.

[@RobertFeranec]

Thank you Zhitai PS: I have just explained Dominik, I do have some materials from our call with Eric what I am still planing to use, but not the exact explanation.

[@marginalamien5710]

Vivement les autres parties de cette série de vidéos. Merci beaucoup Robert.

[@dominikliberda4017]

Awesome video. These two videos were simply amazing. I'd like to see the rest of the call with Eric (or basicaly anything with him, he is really cool!) and how to measure PDN impedance (that sounds quite interesting and something I'd like to try). I wish somebody would teach us this in school...

[@RobertFeranec]

Thank you very much Dominik. PS: I do have some materials from our call with Eric what I am still planing to use, but not the exact explanation.

[@ou81218]

Thanks for sharing the video. Very helpful.

[@RobertFeranec]

Thank you very much ou81218

[@nenharma82]

I'm eager for more! This is awesome and helps so much with understanding what's going on.

[@RobertFeranec]

Thank you very much nenharma82

[@sanketwalopkar1094]

Well I have been watching part 1 and part 2 like episodes of a series. A very exciting series. And the plot is getting very interesting by every episode. 😄 Can't wait to watch part 3 of it. 🙌

[@RobertFeranec]

Thank you Sanket. PS: I have just started recording part 3 .. so coming soon

[@douglasacramer76]

These have been great videos! I'm looking forward to seeing how they did the actual measurements.

[@RobertFeranec]

Thank you Doug

[@Graham_Wideman]

An outstanding series Robert!

[@aniketghosh8812]

wow, this video had so much to learn today. The capacitor behaving as an inductor just blew me away. Keep going, pal.

[@RobertFeranec]

Thank you Aniket

[@nihar0689]

Hi Robert, Pretty nice way of explaining the effect of parallel and series resonance in real life. Wish they taught us all these theories at school with such practical demos. Eagerly waiting for part 3.

[@RobertFeranec]

Thank you Nihar

[@a1nelson]

I appreciate all the time and effort you put into developing this series. Although I was well aware of the formulas and curves for both ideal and real-world capacitors and inductors, seeing them play out in variations in the layout was really eye-opening. Like you, I’m not sure if this new understanding will greatly affect my PCB designs, but I’m pretty sure that it will cause me to subconsciously improve them in small ways. That’s my guess, anyway. I would say that it will affect my decision making, when it comes to single or double sided assembly. For high speed (~1GHz) the benefits of placing decoupling capacitors under processors, for instance, are pretty obvious. However, this video suggests that, even at somewhat lower frequencies, there may still some advantages that could potentially justify the added cost of assembly on the bottom side. Hmm. It is also reassuring to see direct evidence that following best practices really does improve the resulting boards.

[@RobertFeranec]

Thank you a1nelson.

[@rakeshv46]

Hello ! Mr.Robert , Even though i know these concepts earlier I don't know its essence in pcb design, Great Video but I still have some questions to be answered , Hope i get those answers from next part....waiting for it ...thanks for useful video.

[@RobertFeranec]

Thank you V Rakesh Raju

[@harishrao2952]

I always used to think these many things in my mind and it was so confusing but your video really helped to see what a small capacitor and a track can do in your circuit. Really a great video. Please try to upload all your videos as soon as possible.

[@RobertFeranec]

Thank you very much Harish PS: Very similar with me .. I knew there is something going on, but had to put it all together and experiment a little bit to actually see the real influence and importance of these effects.

[@wahidshirdel1119]

Thanks for clarifying these kind of thing in detail.

[@Gengh13]

This series is awesome, keep it going.

[@andreymilovanov8720]

An awesome video, as always!! Thank you!!!

[@RobertFeranec]

Thank you Andriy

[@myhobbies5965]

excellent, i always learn a lot form your videos.

[@antoniocarbajal8009]

Robert, thanks so much to share your knowledge, it is so really motiavtionalfor me, undrstand what Happens in the board... Reggards From Peru

[@ezokaram]

i knowed about XC and XL impedanz but its for me now clearly waht does the Transmision line (Track) has an effect in the circuites even it is a short line and learnd that the best way to place the Cap. near eachothers to minimiz the Noise. THanks a lot my teacher :-)

[@hedleyfurio]

Look forward to part 3 . A few days with a VNA and RLC test circuits is great for understanding these “ passive “ components which are often covered in an hour or two in most courses . Having cut my teeth on Z80 running at 2 MHZ the old days were easy , just ensure all points were connected together . Now we are in the realm of physics on steroids so it’s like walking through a minefield and so many levels of abstraction that hardware and software development has moved toward become system building . Most new designers just buy a working module

[@nikosfarlekas2647]

master degree lessons for free!! Thanks a lot!

[@declanallan885]

something also very important to note about the difference between impedance and resistance is the fact that impedance also takes into consideration phase offset, as a complex number it really carries too discrete pieces of important information and that is the effect on a signals amplitude, likewise it's phase. This aspect of impedance isn't necessary within this context however does become important to understand when you are attempting to understand filter theory, also this type of problem is basically a transmission line style problem, these sorts of considerations of circuit design are also really important in areas such as telecommunications and power transmission systems.

[@amrocomm]

Bro you are the best Now I can understand why some times my microcontroller circuits are not working probably when it is in the real world specially when using transformerless power supply, you can see a piece of ................ Go a head bro you are best

[@RobertFeranec]

Thank you very much Amr

[@vasylchopyk7689]

It is for this reason that I like to arrange garlands of different capacitors around the pins of my microcontrollers. Of course, I always guessed that this is good, but this video perfectly shows how close the operating frequencies of conventional STM32 MCUs to the parasitic frequencies of the components and the tracks with which they are connected. I think in the next video, when we get to USB, it will be appropriate to summarize all this with the phrase "parasitic frequency" which refers both to individual components and to the ways of connecting these components. For example, the input inductance has its own parasitic resonant frequency, and at frequencies from ~ 50 MHz and higher it turns into a capacitance. As a result, it will be possible to say that if all possible "parasitic frequencies" on your board are located above the maximum frequency which this board operates, then everything will work fine, if you do not dig too deeply.

[@JuanPabloCisneros2207]

I do that to, but Sussy Webb and Rick Hartley says that it can't be a solution but a mitigation... I'm have to do som test and see what happen with better power planes an so..

[@Chupacabras222]

Can't wait to see next part to continue where actually part 1 ended. Explanation of that PDN impedance, how to get to that graph which was Eric Bogatin talking about.

[@RobertFeranec]

Thank you Juraj. PS: I do have some new recordings with discussion with Eric on this topic :) I just need some time to put it all together and publish.

[@WesleyLeeYang]

Looking forward to Part 3! In general, I'm familiar with the pitfalls of resonances so I'm weary of placing L-C filters (so I use RC whenever I can in low current circuits), or I put a "DNP" resistor footprint to dampen the resonances if necessary. I never get the time to actually test this in my boards and/or simulate though..

[@RobertFeranec]

Thank you Wesley PS: I would like to do also some testing - let's see if we will be able to do it

[@leeslevin7602]

Brilliant, thank you Robert 👏

[@RobertFeranec]

Thank you Lee

[@p_mouse8676]

This track inductance also explains why you need to match differential track lengths above a certain frequency. They basically just act as delay lines. Nice video, for simulating I would recommend Ltspice 👍🏻

[@RobertFeranec]

Thank you very much P_Mouse

[@xxultz]

I didn't understand why you put a via between the capacitor and the IC pin, if it is a PTH pad. I was curious to see the PDN with that placement, because I can see a different circuit (from the IC power pins point of view) when you put the capacitor after the power pins (like it was in the beginning) to when you put them before the power pins.

[@RobertFeranec]

Yeah, I also keep thinking about this difference.

[@randydireen3566]

Really enjoying your videos!

[@RobertFeranec]

Thank you very much Randy

[@militaryAirforce]

Very usefull chap. of continued dec. Capacitors. I want to see 3rd part pls.

[@samadm9646]

thanks , but how do you make the AC simulation work , ( what is the step to do the simulation in this video)?

[@jorgeherrerasantos7990]

Looking forward to watch Part 3! Now I need to know more about Impedance hahah One question... how do we know at what frequency our tracks will work? I mean how could we know how to optimize our tracks depending on the function of each track?

[@bernard.tomasevic]

Will you do an all-in-one lesson for all the PCB desing recommendations?

[@RobertFeranec]

Bernard, please what exactly do you mean?

[@bernard.tomasevic]

Robert Feranec for example, how to fine-tune component placement, how to place power, ground and signal traces, how to properly set creepage and clearance distances, how to take heat dissipation into consideration, how to properly do layer stackup...

[@JuanPabloCisneros2207]

"And this has nothing to do with clock frequency. It's about the edges." as Rick Hartley says in the AltiumLive conference. It's mind blowing haha

[@myetis1990]

I dont think so, because, if your clk freq rises then edge of the clock has to rise, otherwise you can not get a square signal. So I think that Rick Hartley said like that because it is much easier to depict the integrity.

[@kiranin1989]

@@myetis1990 no his point was don't hang on to clock frequency number because harmonics generated by rise time are different and higher than clock frequency. so 500khz circuit does not been you need to filter 500khz because rise time will generate noise at much higher frequency for that clock.

[@TSRHelios]

@@myetis1990 yes and no. In one hand, if your clock frequency is at the parasitic frequency it has a higher amplitude for that particular frequency. On the other hand, square wave is comprised of all frequency (Fourier's theory), so with square wave you get all frequency across the spectrum. The question is how significant the amplitude is.

[@lucaiodice4629]

If we consider the inductance between the 100nF capacitor and the pin higher, wouldn't be the frequency of the resonance lower if we consider the w=1/sqrt(L*C)? I'm pointing to the lower point at the high frequency where we only consider the 100nF capacitor and the inductance between this and the pin. Thank you

[@alisallam2225]

Great Job thank you for your effort

[@doktortronikelektronikaszk4070]

Capacitance has a negative impedance sign. Shouldnt it be jwL-j(1/wC) - > XL-XC?

[@RobertFeranec]

Yes, my bad. It is a mistake on the website .. and I just copied it :( But still, the results are ok.

[@doktortronikelektronikaszk4070]

@@RobertFeranec yes, results are correct - sometimes math just works as we expect it to work :-) Anyway - good video!

[@sadeghmoradi80]

Thank you Robert!

[@myetis1990]

soo inspiring, thanks. But you did not mention about how to deal with decoupling, is it enough to put 10uf and 100nf next to Vcc pin? I'm sure that this is not enough. We may need to put some more caps regarding noise bandwidth, I think, So The big problem is how we decide noise frequencies? Secondly, I think that the package size of the components affects the parasitic values, but how can we decide which one of the trace parasitics and component parasitics is more significant? By the way, I would love to learn details about ADS to analyze signal integrity and power integrity. waiting for tutorials about them.

[@RobertFeranec]

Thank you Mustafa PS: We will be speaking about some of these topics in future video(s)

[@sagarnavale7856]

Hi, thank you so much for sharing such great knowledge. My query is how to define the value of decoupling capacitor on the basis processor working frequency ?

[@RobertFeranec]

Thank you. I asked Eric about this, I do have a short clip on that topic and I would like to play it in a video from this series

[@jagenbabu3187]

Awesome way of presentation and preparation. Shown the graph behaviour (R,L,C),but target impedance missing in the graph or not calculated?

[@rogerfurer2273]

Thank you Robert, I find these videos interesting and useful. I have a couple of questions: If the ideal is to have the caps between the supply and the pin, wouldn't it be better to leave the smaller cap where it was and move the larger next to it and change the power via location? Also doesn't increasing track width lower inductance? Again, thanks a lot.

[@RobertFeranec]

Thank you very much Roger. PS: I have similar questions on my list what I would like to ask Eric. I may postpone part 3 of this video to get these answers first. And yes, increasing rack width lowers inductance, that is one reason why power planes are much better.

[@tomasbergh]

Wider Tracks have lower inductance AND higher stray capacitance (distributed) to for instance the 0V plane in the inner layer...

[@r.safakarici4686]

Thanks for your nice video. I have a question. Could you answer? Because the higher and lower value capacitance act differently at the same frequency. Such ac 100nF and 10uF. To eliminate this, could we use same capacitance at whole PCB? For example, could we use 100 capacitors of 100nF instead of 10uF capacitor? Is it an advantage?

[@sharana.p5921]

I have a doubt. I currently designing a PCB of 3 kinds of VCC as 12v, 5v and 3.3v. I had setup the layer stackup as 4 layer, L1 as signal layer with 12v polygon , L2 as signal layer two polygons 5v, 3.3v(half of the board), L3 as ground plan, L4 as signal layer. The board doesn't have any critical signal paths like differential pairs. The maximum frequency of all signals is 166 MHz. Would you suggest any thing or this will be enough to do the board. Thank you.

[@RobertFeranec]

That is hard to say. I usually use 4 layers for very simple boards (e.g. breakout boards) and 6 layer stackup for more complex but cheap boards. This may give you some ideas: welldoneblog.fedevel.com/2013/09/17/3-steps-how-to-determine-calculate-number-of-pcb-layers/

[@sharana.p5921]

@@RobertFeranec Thanks a lot. The article helped to give some clarity. ❤️

[@Pedro-rz5dc]

The Eric's book Signal and Power Integrity Simplified is very good and complete about this topic, If anyone else is interested in this, I highly recommend reading it!!

[@ismailovali6368]

Thank you so much Robert, I like you very much :)

[@gojkeee]

Hello Robert. Thank you for that videos about this. But i have a one quick stupid question - i didn't understand why does a current density across the resonance circuit is rising? So, if we have a pdn impedance max point, we will see more voltage drop on corresponding frequency, but i really have no idea about current density. Thank you

[@RobertFeranec]

I have similar questions on my list to ask Eric ... I just need to wait when Eric has some free time for our next call.

[@giovannimezzina2849]

In fact, it is so strange, the behaviour seems more similar to the ripple voltage response. If I correctly remember PDN and power integrity bases, the problem is that the transient current is something like "independent" from PDN. It is "more dependent" on the microcode you run on the IC and the set of frequency normally involved. The problem rises when the "independent" current match the peaks in the PDN profile. There the Z*I explodes giving the enormous ripple we saw in Florian oscilloscope figure. For that purpose, the PDN should stay under the Ztarget up to the roll-off of the clock signal, then can be relaxed.

[@nicoladellino8124]

Very nice video, TNX

[@villetiensuu178]

I think board thickness should not be used at 15:35. Instead trace height should be used. Something like ~0.2mm for example.

[@優さん-n7m]

@20:20, "... because in future the frequencies are just going up and up, the future boards are going to be more complicated for design. SO what is working now does not mean it will work in future. OK? You need to learn all the new things. Even, Maybe now you can get away with not making perfect layout or perfect connections. Maybe in future its not going to be so easy". With all due respect to the vendors, I believe that if things keep getting harder as they are, they might as well just create 3D multi-chip modules where the VRM, decouplling capacitors and ferrite beads are all inside a single massive package.

[@優さん-n7m]

The capacitors are connected in parallel, so even if they start to behave like inductor and have very high impedance at high frequencies, why should it matter to the VCC pin of the IC of interest? I mean the current goes from VRM into the IC, without going through those capacitors.

[@electricblue8707]

After the meeting with Eric where he said 100nf are useless, why are you still using them ?

[@guillep2k]

It would be interesting to see a new Excel graph with the *sum* of the two non-ideal capacitors, instead of them superimposed. I think you'll probable see the W shape you see in the PDN graph.

[@RobertFeranec]

Yes, you would see something similar as the PDN graph (W shape), just it would not include for example the inductance of PCB layout which can actually influence the characteristics a lot.

[@cheemuchoudhary7775]

We used DC for electronic circuits....why noise generated in circuit

[@zek_de_ed6389]

Nice video.

[@RobertFeranec]

Thank you Emrah

[@徐浩泽-e4r]

hi~ I like your video very much, but i have some problems when watch your vedio. May I ask why that some of your videos cannot use the captions? My english is not good so that I need to use captions to assist in watching videos. Thanks very much

[@marv4895]

the orange inductor impedance is just 1.5nH more... or in other words 4 times higher than 0.5nH ^^ what a surprise to see 0.3ohm*4

[@keithsummers1889]

Would you consider upgrading your microphone? You tend to speak with low nasal tones (I assume you have a French background) and it is hard to understand some of your English words. If you could brighten up the high frequency in the sound, this would make it easier to hear the words. Thanks.

[@andreasschindler6077]

👍👍👍👍👍👍👍

100 x LIKE!

[@RobertFeranec]

Thank you Mubin

[@優さん-n7m]

Real capacitor behaves like an inductor at very high frequencies, thus it has a resonance frequency. Real inductor behaves like a capacitory at very high frequencies, thus it has resource frequency. The reason is hidden in how a real capacitor and real inductor is modeled. This appears strange but is the truth. Thus means that beyond a certain frequency that can be called the resonance frequency, the capacitor no longer behaves like short circuit to the AC signal. This is very significant point.

[@amirsaeed9163]

Another issue about choosing right decoupling capacitor! videocardz.com/newz/manufacturers-respond-to-geforce-rtx-3080-3090-crash-to-desktop-issues

[@RobertFeranec]

interesting

[@saisiddharth2675]

I want to learn PCB design How to learn and give me suggestions sir

[@akhileshkumar8753]

If you are really a beginner, try starting with KiCad, it's open source, then as you learn more, hop on to this channel back to learn more about Altium designer.

[@RobertFeranec]

sai, there is a lot of information on internet and youtube - it is possible to learn a lot. The best way to learn is to work on a project - you can come up with your own project. If you have any questions, you can ask on forums, well known is EEVBLOG forum, but we also have forum here: designhelp.fedevel.com/

[@a1nelson]

Mr Feranec is clearly too polite to recommend his own paid courses directly, but I will gladly do so. His Academy courses on Altium Designer are very high quality and impressive in their depth. When a colleague and I took the course a few years ago, the cost was around US$250. So, not cheap. But, if you are serious about learning design - especially for future professional work, I cannot recommend them highly enough. They’re a great investment. For layout as a hobby only, I completely agree with the Kicad suggestion. Consider checking out the Contextual Electronics channel for some Kicad basics. There are, of course, lots and lots of other good channels too. Best of luck!

[@RobertFeranec]

@@a1nelson Thank you very much

[@amirsaeed9163]

@@a1nelson Yes. I recommend them too. he is the best I've seen