"You must Unlearn what You have Learned"

[@thebyteattic]

I think the points are dangerously misleading. (a) Yes, if you can precisely calculate the parasitic inductances of the traces until the decoupling caps, you only need one or two decoupling caps to cancel out the resonant frequencies. But how practical is it to do this calculation? If you can't do it, several decoupling values do help, as the chances increase that you will cover the resonant band. (b) Yes, if cross-talk is, to begin with, not a problem, stitched copper pouring doesn't help, as going from 0.2% to 0.1% is irrelevant; BUT IT DOES HALVE the cross-talk! 0.1% is HALF of 0.2%! In cases where cross-talk is not insignificant to begin with, this can help a lot. And in most practical, real-life cases, we don't have the luxury of spacing e.g. bus lines with 5 line widths; we're lucky if we can get away with one or two. (c) Copper pouring is not just for cross-talk; it reduces the impedance of the PDN and helps with decoupling as well, if one alternates Vcc copper pouring with ground planes. All in all, this hole thing sounds rather academic; it's like professors telling us to use a ground VIA next to each signal VIA... alright, try that in practice and report back to me.

[@DeadCatX2]

Agree with decoupling cap section. Take the smallest footprint your process supports, find the biggest capacitance in your budget, and use that for decoupling power pins. Disagree with some of the copper pour section. Honestly, who would let a copper pour float? Most modern design tools throw a DRC error when copper floats. Including such an example for anything more than completeness is a strawman. You can already make a compelling argument when it comes to using enough stitching vias for the frequency of interest. To answer the question "what problem is being solved" - copper pour is most effective whenever it is used with proper knowledge of the stackup to increase interplane capacitance and reduce inductance in the return path. If your PCB is four layers or more, you are likely going to have e.g. layers 1/2 closely spaced and layers 3/4 closely spaced, while layers 2/3 are a significant multiple of this. In such scenarios, well-stitched copper pours of ALTERNATING polarity to the closest reference plane will dramatically increase interplane capacitance (by integer multiples). Alternating polarity is key; if your copper pour connects to ground above a ground reference plane, it won't be very effective. Interplane capacitance is the main way to decouple the PDN above several hundred MHz. Copper pours can also facilitate the passage of return currents that are referencing the alternate reference plane from a more distant layer. Consider a signal on layer 4, referenced to a positive plane on 3, switching to a signal on layer 1. It would see much lower inductance passing to a power pin through a copper pour connected to the positive plane. Without the power pour, the return current would travel up to layer 1, through a bypass cap, down through layer 2, back under the trace, back up to layer 1, and into a ground pin. Such return currents only pass through one via with a copper pour, and three vias without it. Again, alternating polarity of the adjacent reference plane is the key.

[@AhmedHan]

About copper fills: We don't add the copper fields. We etch it where we don't want it. Therefore, the real question is: What problem does removing the copper pours solve?

[@okiefreemen]

You are correct, and the video and altium are wrong and did not debunk anything, the experiment he did was invalid, removing copper for no reason is the real problem. I wish people who don't know what they are talking about would not pretend to be experts debunking myths, when they are actually spreading exactly wrong information.

[@thebyteattic]

@@okiefreemen Ditto

[@engsam7759]

amazing lecture , please bring him again to talk about the rest of the subjects he teased at 2:44 . Especially the last three subjects : myth of ferrite on power rails , myth of 90 degree bends and myth of matched length traces

[@orientaldagger6920]

Why don't you buy his book and you can read all about it.

[@douggale5962]

Super low inductance capacitors (SLIC) have lower values, so there is a kernel of truth in the advice of using smaller values. This video taught me that you go for low inductance capacitors, and just being a low inductance capacitor will force its value lower, but you still want as much capacitance as you can get. And use 10V caps for 5V rails, not 6.3. 6.3V caps are for 3.3V rails, I guess.

[@gudimetlakowshik3617]

People need to have the patience to watch this. It is definitely worth it. Loved the video, huge respect to Eric...!!

[@0x07AF]

Rick Hartley has emphatically expressed the exact opposite opinion regarding PWR/GND-connected copper pours and stitching vias, including on the outer layers. I think the data he provides and his explanation regarding the benefits you get from the increased capacitance, significant decrease in inductance with likely EMI improvements provide a much stronger argument than this one. He also explains and shows how the lower impedance can help a lot at the higher frequencies where bypass capacitors are inductive. Eric primarily hyperfocused on microstrips and crosstalk in his argument here. You just need to avoid adding copper pours anywhere near microstrip lines. Problem solved. Also, I don't know any professional layout tools that will let you get away with accidentally floating copper islands unless you just completely avoid or ignore DRC checks. Otherwise, I think this was an excellent presentation.

[@montvydasklumbys7584]

I have a similar opinion. Especially, since when designing 4-6 layer PCBs it would be nearly impossible to have good design without having copper fill on the signal layers.. I mean, we gotta have big power planes to not have voltage drops, big GND planes to have a stable reference and short distance between GND and power plates to increase capacitance, thus placing them in between the short dielectric layer. Now add that we cannot pour copper over signal layer and that signal layer needs to be close to GND layer and our 4 layer PCB becomes... signal-GND-(core)-PWR-GND, we can only have 1 signal layer on a 4 layer PCB... The circuit would have good signal integrity, no EMI issues but oh boy would be quite a waste! In that case the only solutions to this would be to either have core just as thin as the dielectric layer, which would force the PCB become very thin... Or use a lot more layers just to be able to have 1 more signal layer.

[@okiefreemen]

Rick is correct, and this guy in the video is exactly wrong, and he should stop spreading myths, he debunked nothing

[@DeadCatX2]

Bingo. Pour polarity should alternate with the nearest reference plane in the stackup for the reasons you cited.

[@thebyteattic]

Ditto.

[@robiniddon7582]

Both are right. Don't add the copper pour if you don't need it. If you are trying to squeeze an 8 layer design onto 4 layers then maybe you need it. Don't just add ground pours everywhere as a matter of course. If you understand what it is you are doing and why you are doing it, then of course it's a powerful tool. E.g. sig/pwr gnd gnd Sig/pwr 4 layer stack up.

[@Retinatronics]

This is the second time I am watching this. So much to learn.

[@mars5617]

I think the real reason to pour as much ground copper as we can is to reduce impedance. As you know we are making our calculations based on ground referance so if ground copper is small , because of increased impedance, there will be more voltage drop on it so it will change the behaviour of circuit.

[@orientaldagger6920]

As clueless an answer as I have ever seen.

[@robegatt]

@@remy- I think he's talking about ground as reference planes for return paths.

[@rbrucecarter]

There IS a reason for copper pours, but it has more to do with the environment than it does circuit performance. Etching less copper will produce less toxic copper compounds that have to be dealt with.

[@theincapable]

And if you etch it yourself, your etching solution lasts much much longer.

[@Zachariah-Peterson]

@50:30 0.35% to 0.25% is a 29% reduction in crosstalk... Looks like a pretty good reduction to me, but the point is that it was already very small. 0.35% of a 1 V signal is 3.5 mV, well within noise margins for digital circuits. It can be ineffective as shielding between closely spaced traces where crosstalk is a problem, and if used incorrectly (left floating or with incorrectly spaced vias) it makes crosstalk worse. You might take crosstalk that was already negligible and make it more noticeable. Like many design decisions, it's been poorly communicated and it is not a magic bullet for signal integrity problems.

[@NathanSweet]

It's small because he has 5x spacing. I wish I could find such spacing on any of my boards. Note he didn't show a medium number of vias, just "many" and "not enough" (floating is obviously bad).

[@Zachariah-Peterson]

@@NathanSweet I think it underscores the point that if you wanted to include stitched pour or a guard trace with stitching (they are the same thing), then you already have to apply at least 3W spacing in order to fit the trace, and this will make the crosstalk low anyways.

[@barkingmadd9631]

Hey dammit, I said I wasn't going to sit here and watch an hour and 17 minutes of some video, but an hour and 17 minutes later I'm still here. How dare you create such engaging content.

[@vladlv2]

Excuse me, I will still add GND pours on signal layers on 2 layer PCB, I never pour in-between tracks... use stiching and use higher clearence to signals 3x track spacing etc. solid blocks of ground are still very usefull for creating better ground connection, because on 2 layer pcb ground regions could alterate between bottom top etc.

[@JeromeDemers]

to answer the question @41:53 it's because it's faster to connect the ground with ground plane then connecting each ground one by one.

[@PedramNG]

That was fascinating, I would love to see more from this guy. 😍

[@Bornachiever17]

Please respect him he is very reputed legend in this industry he is mr. Eric bogtain professor

[@va-josefranciscomontoya866]

Finally watched from one of the signal integrity gurus. Thank you for sharing.

[@AltiumAcademy]

Welcome!

[@mdesm2005]

At time stamp 43:30, is there a "ground" reference plane below the two strip lines for the return current ? If there isn't then that could be why you add copper fill. To provide a return path. Then in the second example, with a "fill" between the traces, he says "We're going to keep it floating" . Which contradicts earlier statements about coppers fills. Later he says "we can assign it to the ground net, but it's floating". What does that mean?? The third case is described as having a "gazillion vias" to ground. This sort of baby talk doesn't inspire confidence. Overall, it's a pretty loose presentation. If there is no "ground" reference beneath the two signals, then add a GROUNDED "fill" near the signal traces to provide a return for the current.

[@Rotwold]

I think he's talking about the ground fill between two traces that isn't physically connect to the rest of the GND nets. An isolated area of copper with no connections. That's why he uses gazillion via to connect to the ground plane. But I do agree, there isn't a clear reason why ground pour introduce negative effects on the board and not many reasons why avoiding is better.

[@happyhippr]

thanks altium & eric, nice quality content.

[@mikal_1]

Comment for the "copper pour after routing" segment. I wonder what the crosstalk would be if the two signal lines were closer and what the crosstalk would be if you had a ground trace (not floating) between them. Like 8 mils spacing between them. Would anything change or would the result be the same?

[@roliveira2225]

Excellent lecture! Congratulations!

[@鄭峻杰-i2k]

Thank you Eric, it's an amazing tutorial video.

[@edouardmalot51]

Interesting. But for capacitance in parallèle, the point is not only at the highest frequency. When you put capacitor with differentes values in // out get also different minimum impedance at different frequency, so you get a larger low floor of impedance

[@PumkinsDaddy]

Adding copper to the voids on a signal layer assists in the etch process, also signals on the inner layers. Copper balancing. Instead of a solid copper it is better to add copper thieving. Small copper patterns (diamonds, dots) that are isolated from each other to avoid causing unwanted current flow.

[@okiefreemen]

This guy in the video is totally wrong I his argument against copper

[@timun4493]

i like to add copper pour to all my signal layers, especially on the outside layers to help conduct and radiate heat away. i do however use design rules to keep these pours at least 3x height above plane away from my controlled impedance net classes, 3x might not be enough but shouldn't whatever spacing was determined not cause crosstalk issues also prevent significant coupling of energy into those cavities ?

[@pattherat5378]

Yuuuuuyyyyyyyyyyyyyyy

[@VndNvwYvvSvv]

Yeah, it's more about passing EMI/EMR testing.

[@stm3252]

Excellent lecture from an excellent engineer!

[@MrJetra]

Is an electrolytic capacitor a good choice for decoupling 50ns? That is not what I've learned. But I might need to unlearn that as well.

[@hunJ1207]

isn't the aim of adding different value capacitors to reduce the inductive effect of the capacitor beyond the resonant frequency?

[@EliteHEAD]

What do micro-ferrets have to do with capacitors?

[@joesmith-je3tq]

At 17:00 in, you show the breadboard. There appears to be a ground loop formed around the two sides of the breadboard. At 19:30 and 21:45, the scope probes appear to have no reference. The long ground straps are are dangling on the bench and I found no ground wire wrapped around the tips. As you start to collect data at 20:00 / 21:50 in, the scale is 50ns. I suspect a lot of the problem is the scope not being properly connected. Maybe I just can't see the ground loop but I was actually expecting you to talk about the long ground lead.

[@MattNeighbour]

If you look closely you can see a ground spring around the tip connecting to an adjacent breadboard ground hole, the loop area is very small and signal integrity very good.

[@robegatt]

He uses the ground tip to reduce the loop... standard practice.

[@MrHeatification]

Where is part 2 ?? please bring him back

[@Electheo]

It seems that pcb trace impedances are very important to know during design. Can you measure it using a LCR meter on the actual board, and is that accurate enough?

[@Zachariah-Peterson]

Yes it is very important to know. You cannot measure trace impedance with an LCR meter when the trace is in an assembled PCB. Maybe you could do it with a test board and some fixture that attaches to a pair of connectors, but it will probably not be accurate. The correct way to measure trace impedance is to place a long uniform trace on a PCB and perform a TDR measurement using matched connectors and a reference terminator at the other end of the trace. This will only give you an accurate impedance measurement up to some maximum frequency in the GHz range.

[@AMalas]

The problem im trying to solve by flooding the bottom layer and connecting it with GND is changing a signals reference and its return path. Say I have a 4 layer s/g/p/s stackup, and I have a signal go from layer 1 to 4, I cant just connect a via from layer 2 to 3 alongside of the signal via, and its not realistic to have two vias and a capacitor per signal via. I know in another video you recommend routing power and just going with s/g/g/s, but that is not practical where you have hundreds of vias going down to 3v3. As a compromise, what about pouring power on the bottom? As long as no thin strips or island exist

[@TooHear]

What would be crosstalk result of the last simulation exercise, using more VIAs spaced at a pitch of 1/10 of lambda = (((c)/(sqrt(er)))/0.5)*tr. Assuming: c = 0.3e9 m/s, tr =0.2 ns and er = 4. Assuming BW = 0.5/tr[ns]... I would think the crosstalk should be lower, but it would be interesting to see how low...

[@dawiducsinnovation4113]

A very smart man- especially since the very first slide of an sch he shows is of something done on Eagle cad🤣 I have spent the past two days trying to recalibrate my brain to work in the disjointed Altium way of thinking and all I got for my efforts is more frustrated.

[@emmanueloluga9770]

Altium's problem is exactly their benefit/advantage as well. Somehow they are stuck in this sort of "design" process revamping that plagues the non-technical visual world of design. Thus this translates to them trying to revamp their UI every year at the expense of routine ECAD designers are more accustomed to due to the scope and breadth of information required and involved in electronic design. Thus it's exactly also their benefit, they will always add some convenient new feature that does improve and speed the process in one area but slows down workflow in another due to the revamp and thus incurred learning curve.

[@dawiducsinnovation4113]

@@emmanueloluga9770 if it ain’t broke... but the programmers can’t charge money for that. If you want to throw up a little- go to the Altium homepage, scroll to the bottom and read the “about “ page. They don’t give one singular flying f about their users. And why can I rotate a part on the sch with the space bar, but I need a full sing and dance number to do it on the pcb!?!?🤯

[@emmanueloluga9770]

@@dawiducsinnovation4113 Hey ok, ok..you right...the PCB workflow always almost makes me wanna puke lmao. The rotating thing is also a particularly big issue of mine as well. I think there most definitely is some sort of division between the realites of the programmers and marketers

[@thebrakshow7415]

@@dawiducsinnovation4113 I know this is old and surely you figured out the rotation issue in the pcb layout... but incase some else is having the PCB rotation issue: Tools->Preferences (or hit the cog on the top right) -> PCB Editor -> General. Under "Other" there is a field for "Rotation Step". If that is set to zero you cant use spacebar to rotate. Set it to 90 or whatever you like. Crazy how such a simple setting can make life much easier.

[@Hadi-zw9mb]

Hey Eric, great explanation, thank you. I have a question about copper pour. What if outside of coupling lines is poured? I think it reduces cross-talk.

[@maksymkloka7819]

I have been telling all my junior engineers NOT to use stagged in value capacitors, ... instead use multiple capacitors of same value.

[@simonndungu1196]

Masterpiece tips and tricks, Thanks Eric!

[@lileffects]

So what is the solution to making sure there is a return path for signals? If I have a two layer board do I need to stick with only one routing layer and have ground on bottom? If I need more than one routing layer am I jumping to a 4L board by default?

[@kwastek]

Yes

[@robegatt]

They sell them at the same price... 4 layers is minimum nowadays.

[@lileffects]

@@robegatt This is true. My issue is that it becomes a "If you give a mouse a cookie" type of situation because 4L stack-ups aren't all that great either so automatically a 6L stack-up becomes less of a compromise.

[@robegatt]

@@lileffects 4L are excellent for non high-speed stuff, just slow down the edges with series resistors if some ics switches too fast. Even the power-layer return paths capacitor vias are for very steep rise times. Makes no sense to me using a 4L for highspeed. Keep in mind that these videos are ALL about high speed and in that contex a lot of things that are STILL valid at low speed must be avoided/changed (e.g. guard traces are effective for analog shielding and low noise, but have to be avoided at hs)

[@3ATIVE]

I really wanted to watch this video/tutorial, however... For a guy talking about suppression, Ironically had a extremely loud high frequency "whistle" to his Sibilants!!! - 8 mins in and I've already got a headache 🤦‍♂

[@mohinderkaur6671]

Really great talk! Bob Pease died on the same day as Jim WIlliams

[@fatihozbakan7772]

I think i am the first one watching you, while i am drinking Turkish Raki :)

[@timun4493]

shouldn't a higher value capacitor of the same size even have marginally lower inductance because individual plates being closer together ?

[@saeidyazdani]

Good stuff!!!!!!!! Thanks for sharing :)

[@abdulmaguideissa]

@ Copper Pour After Routing: What if the design is only two layers for the signals, power, and ground? Will it help to remove the copper pour islands?

[@g6axf]

You don’t add cu fill you etch it away so by leaving it you have one less process to do

[@Zachariah-Peterson]

He means to add it to the design. Also etching the fill is not one additional process, etching an entire layer is a single process.

[@syamakrishnans]

quality content🤩

[@preetham56]

Thank u sir

[@CaseyHancocki3luefire]

the PCB mfg wants to etch less copper out, so if you don't pour copper they will complain.

[@tr3547]

I totally get what he's saying. But here's the reason I add copper fill because it's easier and cheaper to fabricate. Order 10 million boards and then do the math.

[@jkvideos6826]

Does anyone know what is the equivalent trace width and copper thickness of breadboard inter copper metal, just curious 😂

[@douggale5962]

A breadboard would be equivalent to very low trace width. Solid copper is outrageously conductive. You would be amazed how many amps you can carry on a 1mm trace with tens of millivolts of voltage drop. The problem with breadboards is that they add tons of parasitics, the resistance isn't really the problem. If you want to draw a schematic of your breadboard, you'd put an inductor and resistor in series between each hole, and you would put a capacitor at regular intervals between adjacent bus bars. A PCB has the same parasitic inductors, resistors, and capacitors, but the values are much lower.

[@science_electronique]

عظيم

[@AbdullahKahramanPhD]

This video is underrated

[@jeremyglover5541]

Hmmm, I think your copper pour and crosstalk section is disingenuous. In analogue amplifiers where you are trying to minimise crosstalk. 0.2% is pretty significant. That is only -27dB Of course adding floating copper between them is going to make things worse ... as you said, who does that? so then you add stitching vias, like most people would do and you cut your crosstalk almost in half!! is it significant? you bet your ass cutting it in half is significant; that's a nearly 50% reduction. if you have that on several traces, that adds up pretty quickly. You used an example that is stupid and use that as a means to discredit it across the board. There are no magic bullets and i'm not championing pouring copper into every gap, but there are good reasons, especially in mixed signal boards, where you may have polygons of power and ground pour surrounding components for decoupling to lower inductance and dissipate some heat (many components have the powerpad tied to ground and having local decoupling decoupling to an island of gnd, along with signals and feedback loops that you want to keep on the surface for the same reason.

[@okiefreemen]

Hard to trust this guy when his argument against copper pours is exactly wrong and backwards, just like altiums view on it. All layers started with copper to begin with it was never added back in (altium is wrong in it's legacy design philosophy on this topic) It's not poured back in. And yes the copper on the signal layer helps just as he admitted after making a pour 😂 argument against it. And his test case is invalid, those signal routes would have had waveguide copper on the layer underneath anyway, so it would have never coupled to the copper in the same layer to begin with, this guy being an expert should know this. Glad most of the comments in this video are correct, the video is wrong. Altium has been wrong in copper pours since they began as a company, you start with boards full of copper and then remove copperz Altium thinks you have to pour copper back In wtf 😒