Position of PWR and GND Planes in Your PCB Stackup Makes a Big Difference ...

What do you think, is there a difference if you place PWR and GND planes close to the component layer vs. when you place the planes far away? I was very surprised ...
Links:
- What is The Best VIA Placement for Decoupling Capacitors? • What is The Best VIA P...
- How to Decide on Your PCB Layer Ordering, Pouring and Stackup (with Rick Hartley) • How to Decide on Your ...
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[@mohammad.htarokh2891]

the reason the placement of the decap plays a role on a 4-layer stack-up is the fact that the decap is the only source of charge for transient currents you need for the power delivery at high frequencies and there is a radius it supports the transient current with a low enough impedance not to cause excessive voltage drops is determined by the rise time and the stack-up material dielectric constant. However, in the 6-layer board, since you have closely spaced power and ground planes, they tend to have high inter-layer capacitance which you do not have in a 4-layer board. As a result, the placement of the decap is only important at lower frequencies where the decap(an LC network in reality) is actually a capacitor. At higher frequencies, as you see typically above 200MHz the transient currents are supplied by the big inter-layer capacitance distributed around the board. It lalso indicates that the decaps have actually no impact in helping with high-frequency power delivery. As Erik Hartly said, have power and ground plane closely spaced close the surface of the board in layers 2 and 3 for example if you have high-speed signals(high datarate) and or chips running above 200MHz no matter if you have 6 8 10 or even more layer.

[@str8upkickyaindanuts289]

Great video Robert! One more layout that Rick suggested for the 4 layer stackup was to have the reference plane on 1 and 4, so the stackup would be (ref)-(sig/pwr)-----(sig/pwr)-(ref). Then in another lecture by Eric Bogatin, he suggested routing power rather than using a plane. Applying these suggestions, along with the completely paradigm shifting knowledge of field behavior within the layers (return via placement in layer changing signals), I have been having good luck with mixed signal designs using JLCPCB 4 layer boards. It would be great if you could run a simulation of the aforementioned stackup, I lack the skills, software and general understanding of setting up such a simulation. I struggle to find the words to express my appreciation for the knowledge you spread by uploading such great content, with your help I have been able to better understand and design my board layouts with notable differences in noise. Where before it was a simple task of making my circuit fit and look orderly, now it's a thought experiment on return currents, field paths, cross talk, trace placement, ect... But rather than the goal of better understanding, I'm actually having appreciable results. Thank you!!!

[@fabianluttenberger7153]

I started PCB design about 2 years ago and I am now at the point where I can even offer these services to customers. I learned many things through your videos and trainings. So thank you a lot for that and please keep creating this valuable content :)

[@codedesigns9284]

Blew my mind Robert! I knew (Based on Rick Hartley’s teachings) that it would make a difference, but that much? Yeah! Thank you for providing these helpful videos!

[@hansibull]

Excellent video as always, and very useful information. I was laying out a 4-layer board when you uploaded this video and swapped two layers based on your conclusion. Thank you for taking your time to make these videos!

[@aitelhajreda7867]

I'm watching your videos. they are all interesting and very informative. Thank you for taking the time to explain everything clearly and for making these simulations.

[@22icyo]

As always, very clear, nicely explained and quite informative. Indeed "interesting!" haha

[@RobertFeranec]

Thank you very much 22icyo

[@tufanpars]

Very interesting video. Thanks Robert. Actually I wonder how you test DDR memories after finishing your design. Thanks.

[@RobertFeranec]

@@tufanpars Personally we do a lot of testing (I do not have expensive equipment - so we run stress tests in different conditions). But I am working on videos to show DDR4 simulations and ... maybe ... if we are lucky, we may also see how memory interface can be measured.

[@tufanpars]

@@RobertFeranec It would be great. Thanks.

[@jeff-oi7cl]

@@RobertFeranec Thank you! Best pcb videos on youtube!

[@saeedkizzy]

Thanks Robert, I learned a lot from you videos.

[@arriemulder9803]

Amazing Robert. Thanks a lot. Extremely relevant to what I'm currently doing.

[@RobertFeranec]

Thank you Arrie

[@Music_Engineering]

Very surprising results, interesting and informative video. Thank you! :)

[@RobertFeranec]

Thank you combatcello

[@dmitry.shpakov]

Thank you, Robert!

[@vigneshwarb18]

Much Interest and very Useful, Thanks You.

[@danielcotiga9854]

Nice video. Thanks alot to sharing your tests with as

[@_Jkobson]

Роберт открыл для себя конденсатор собранный из платы. it may sound strange, but try to calculate the value of the resulting capacitance from the board stack, and compare its value with the value of the installed capacitor,I believe that for the 6-layer case, their values will not differ by more than an order of magnitude

[@MrSemperfidelis225]

Robert dellyvery another great vid! Thnx. I love your accent dude!

[@patrickmagee774]

Thank you for a great video.

[@karim1485]

Awesome as always, I wish you would do more about power electronics and less signal 😂 (Personal taste, I am still learning a lot and using your knowledge in my PCBs. Thank you!)

[@m4l490n]

Very interesting video!! These type of videos are awesome!! Very informative. Well, I can conclude that the design can perform better and be more forgiving only by placing the power planes Very close together and close to layer 1 (where the components and signal tracks are).

[@siddharthmali5841]

As always great video.

[@RobertFeranec]

Thank you Siddharth

[@ismailovali6368]

Thank you so much Robert, I like you very much :)

[@michaelk.1108]

Great topic. Very useful to see the comparison! Thank you, Robert! Sometimes hard to realize to bring the power plane closer to the chip, e.g. if you use microvias and have many signals as you know. I will have a look at recent stackups and think if I can improve it. I should try to convince my children to subscribe your channel to increase the number of subscribers...

[@billimew7496]

Thanks for the beautiful video. However, i am curious to know what would happen if we use different types of capacitor and their parallel combination.

[@robertdixon8238]

Very interesting video. Thank you for taking the time to set up and document these simulations. Can you please run a simulation showing the effect of via diameter for the 4 and 6 layer stack ups? I wonder what impact this has for RF components, operating above 1 GHz? I don't expect they will have internal capacitance.

[@juliatruchsess1019]

This is great stuff. Now for the next step I'd like to see how much improvement is made in the "6-layer 45" by adding stitched copper pours in the signal layers to reduce power-ground impedance per Rick Hartley's recommendation.

[@denes44]

I was waiting for a recommendation for the best 4 layer stackup to use.

[@superciliousdude]

One thing closely related that I noticed, which doesn't show up in simulations is that larger footprint capacitors behave very differently from smaller footprint capacitors (even at the same nominal spec) in the frequency response curves. Its often easier at the lower frequencies to lower impedance using physically larger caps even at the cost of more board space and distance, and vice-versa at the higher frequencies with small caps paralleled at close spacing. Had weird start-up problems on an Altera FPGA design due this very issue a few years ago. Fascinating video as ever Robert. Much food for thought.

[@Konecny_M]

Another good trick is using feedtrough capacitors (X2Y) for decoupling. Much better performance for the package size.

[@okiefreemen]

It's because the larger capacitors have higher capacitance for the same rating, volt deratings drops your small caps by %10-%40 this is why you had start up problems you probably had voltages rising faster than vdd in some places.

[@jer_h]

I would be interested in seeing an analysis of the cheap 6 layer stackup at places like JLC (2 cores + 3 copper/prepreg pairs), what would be the best configuration for that? Great video.

[@RobertFeranec]

Thank you Jeremy. I may try that. PS: I would like to say, this topic may be super important for chips with very high speed interfaces, but for normal boards, it may not be so important nor critical.

[@simongustafsson2528]

@@RobertFeranec Hello Robert. What do you define as very high speed interfaces? Which frequency? Thanks in advance

[@DRawwrrr]

@@simongustafsson2528 it's all about the rise/fall rate of the edge ;)

[@zhitailiu3876]

I've been thinking for this for a while, thx again Robert! However, I still have some problems concerning pouring ground on top and bottom layers as Rick suggests for many years. 1. As top/bottoms layers are component layers, the grounds being poured would have lots of "holes", this means that signal tracks, below or about top/bottom layers, have to somehow avoid these holes, in order to keep the fields tight. This is probably not so difficult to do, but definitely more difficult to do with power pours or regions living together with these two signal layers. Or is it okay that power pours/regions across these holes. 2. I have problems envisaging how energy is transferred while it leaves from a pin and directly to a via and then goes up/down to the signal layers close to top/bottom ground layers. First as energy is still in the package, okay it's of course referencing to the ground right beneath the chip. However as it travels right to the pad and then continues to the via, it must be referencing to the ground 'in the co-planar way' (note this means the ground pour clearance must be somehow set to a small value). It seems to me that if the signal goes directly to the signal layers right next to top/bottom layers, it doesn't need ground transition via. Do I understand this correctly? Ever since I watched Rick's video presentation on the layer stack up of 4 layer board, I've been using sig/power, ground, ground, sig/power layer structure on 4-layer board, and it has been quite a success comparing to the usual signal, power, ground, signal stack up. However, as my boards are getting denser and denser, I always want to try pouring ground on top and bottom layers. Unfortunately I haven't seen a reference design using this stack up. Does anyone have any idea on this?

[@Nik930714]

Hi Robert, i loved the video as always. One thing that will probably be interesting is a simulation of just the power planes power delivery, with no caps. I know that the one with the poorly positioned cap (i forgot the number) is the closest to what i'm describing, but it will probably be interesting to see what difference the caps make. Thank you for the great content.

[@stephencapelli8565]

That's also what I'd like to see... During all the video, I was thinking about Rick Hartley on Altium Live, and different information stating that your plan is your best capacitor! So what if there is no capacitor at all? Also, Robert, do your simulation take into account the placement of the load on the top layer? I was wondering, since vias are "the thing", and in your prev video placement on top or bottom did not change anything...

[@RobertFeranec]

@@stephencapelli8565 I am wondering the same

[@kennethblaabjergfog2197]

Great video, but there is one thing missing. You showed us the huge difference between having GND and PWR on layer 2 and 3, and having them on layer 4 and 5. But what if you add in an additional GND on layer 2 (which you would most likely do in a real stack-up).

[@johnk1803]

Hi Robert! Very nice video! Great job! So the stack-up is more important than the placement in general.... Agree? Just want to priorities my workflow.

[@IgorChudakov]

Robert, could you show vias placenents for the best case - light blue lines on the right side? And yes, it was interesting result for the 6 layers, that allow putting the caps around the chip without going to the botton side assembly.

[@MrSemperfidelis225]

Very interesting as always. What size MLCCs are you using? The three examples around 21:30 that are so similar results... could it be the package is so small that the vias are concidered close even if placed worse case? Kind of like the PWR - GND layers when they are close as in the 6layer stackup, the differences are smaller between the various examples because the interlayer capacitance is making a big enough difference to compensate the layout differences. As the distance between GND and PWR plane increases one would expect bigger differences between the various layout examples. The cap - via - load loop begins to see thepart dominate over the MLCC's own inductance, that's when layout and via placement becomes more important. ?

[@myetis1990]

great job Robert, Does the difference between 4 and 6 layers stacks mean that the more ground&power plane the more immunity? Btw If you prepare how it works video series, It would be very appreciated maybe about picking the right charging IC, audio codecs, ethernet controller ic, FLASH+DRAM Ic interfaces, LCD interfaces

[@andreneves3597]

Great video Robert. I have one question. What is the difference between price of this 4 and 6 layers pcb? Because when we are designing, sometimes we need to make cheapest choice, but not the best option. Thank You

[@johncook538_modelwerks]

One thing I'd be interested in is the capacitance between the power and ground planes. Obviously it changes quite a bit as the insulator thickness changes so I'm wondering if plane capacitance is adding a significant amount of capacitance to the entire circuit.

[@marcinfisior1932]

Also interesting that there is no difference between 4&6L stackup in best layout 35. Its interesting that In this case in 4L stackup, the top ultra wide power plane and ground make low imedance power path. So in this case you can have low cost 4L design.

[@hjups]

Very interesting, though not surprising after the last video. Though, the far away placement result was unexpected. Have you seen the decoupling capacitor layout on the Zedboard? (Zynq 7000 FPGA dev board). I always thought it was insane, since the decoupling capacitors were placed neatly on the top layer away from the FPGA rather than directly under the pins (it still has a few under the FPGA, but those are for reference termination / decoupling and not for power). But given the results you showed, they probably have power and ground on L2 and L3, and that's how they were able to get away with that layout. What's even more interesting, is that the Zynq 7000 has an app note from Xilinx stating that very low ESR is required for decoupling. Perhaps the power / ground plane placement was able to mitigate the need for such decoupling as well, where the note is for the "general case". As for the via placements around the capacitors, I would guess that the rule of thumb is for the general case. Sort of like "it's too complicated to explain stackup ordering, so if you do it this way, it should be sufficient regardless of the stackup." Did you also compare the via placements for the 6 layer 45 case? Does the via placement make a difference there, or did moving to 6 layers make the placement irrelevant?

[@luigilavitola]

The Zedboard is really different. It is a 10 layer board that has ground on layer 2 and 9 and power in the two central layers, this makes me crazy because it is really different that what we saw here! But it works, I don’t know why but it works!

[@dannyphantom4point0]

I would be interested in how layouts 14, 31, 55 differ on the 6 layer stackup with planes on the bottom. I think the differences in via inductance would be more apparent

[@apurvawalunj3407]

Can you make a video on how to decide, whether to use microstrip or stripline based on different circuit interafaces, like DDR, PCIE, I2C, SERDES, USB3.0, etc

[@Muftat2ify]

Nice video. What I do not understand in the 4 layer stackup the components and PWR/GND are as close as the 6 layer stackup 23. Why is there a difference?

[@satkalkur]

Hi Robert , When you say I ran simulations , Do you run simulations on the actual hardware or which software do you use .? Which Software do you recommend for the circuit simulations.? Thank you

[@onfield5164]

Nice one..but tell me the link I can't download the software I can use to design my board

[@yasirshafiullah3016]

Can you guide about 2 layer stack? where the top layer has power traces and ground plane and the bottom layer has ground plane.. The board only has power controls i.e has a regulator. Is it necessary to add vias in that board. Sandwitching between top and bottom layer? if you can guide about 2 layer board layout techniques where signal is not there. etc.

[@YummyMercury]

I suspect that the very small differences between via positions in the 6 layer stackup has to do with how loop area is being determined. if the distance between the power and ground plane is small, then the loop has an area that is the product of the distance between vias and the distance from the capacitor to the planes. When the distance between the capacitor to the planes is very small, then an increase in the distance between vias has less of an effect.

[@Kefford666]

So there were some that got worse as you went from 4 to 6 layers? What would be the best 4 layer stackup then? Maybe: Power/signal Gnd Core Gnd Power/signal

[@saucebosspl]

How do you think I should build my stackup in a case of 4 layer mixed signal audio PCB?

[@exoops]

Hi Rob. Do you know if there is a way to reverse-engineer the a 6 layer board in order to make a schematics? For example if there is no information available from the manufacturer but the PCB is physically available

[@paulpaulzadeh6172]

Robert , @17:06 over resonance frequency 10 Mhz in this case , you don't have capacitance anymore, at 100 Mhz your capacitance become inductor !

[@shahzaibshamim6524]

Hello Robert, I need some help regarding cross probe and placing decoupling caps under under cpu. I am using altium 21.1.1

[@pasjawielkiejczestotliwosc6108]

What about this 4 layer stackup: 1.Signal, 2.GND , thick core for example 1,2mm, 3.VCC, 4. Signal plus GND polygon plus stitching vias? Distance between 1 and 2 or 3 and 4 layer 10 mils. When design is cost effective.

[@IgorPshynyk]

I often use a set of 1nF + 10nF + 100nf capacitors, since each rating has its own optimal frequency for operation. Moreover, the lower the denomination, the closer to the chip. But it turns out that the main evil is inductance in the via channel.

[@MrSemperfidelis225]

I used to do that too, we all did. But see some Eric Bogatin, Rick Hartley, oh I forget the names ther are many....Robert even has some of them on his videos as guests. the problem with that decades old technique is the resonances this most likely creates. Besides with todays MLCCs we no longer need the little fast guy, they are all fast (depends on how fast of course).

[@kentswan3230]

differences between 6-23 and 6-45 make sense because of the transmission line distance between the component and the planes. I wonder what would happen for decoupling capacitors on the front and backside for an 8 layer board with gnd/power on 23, and 67 with the power and gnd planes coupled

[@RobertFeranec]

Maybe something to try next ...

[@kentswan3230]

@@RobertFeranec I was thinking the same thing. I note that for LGA's and BGA's the decoupling caps necessarily are on the backside to the board while many other components have their caps on the front side. On one of my RF designs (in Altium), I've fretted about decoupling cap placement and was pleasantly surprised that my default 1mm 8 layer board stack-up (sig, gnd, sig sig pwr sig) worked so well. Only thru vias were used, The poured grounds on the top and bottom layer were pattern-stitched to the layer 2 ground plane. RF to the antennas were coplanar waveguides with stitching with the RF and USB trace impedance calculations were dead-on calculated using ICD Stackup's coplanar waveguide capability. Additionally, from a placement point of view with the number of layers in the stack-up cost-constrained to limit the use of buried, blind and back drilled vias we are left with mostly through vias. Admittedly this constraint can limit the performance of a PCB. These simulations show me that there are surprising methods to accomplish our performance goals without driving the board cost up excessively. I really like the way you use these tools to explore what actually happens. Some of the results are somewhat counterintuitive until you think about the physics involved.

[@SukramNotna]

I think Kent has the right thinking - the impedance is getting higher of course if u increase the distance between your top side component & its traces to the GND underneath. So I guess be careful not to mix up two different effects here. Putting power planes close to GND planes is one thing but putting your reference GND plan far away from your top side is another. And it seems that effect could dominate? First I thought its the length but Kent lets me thought about it. ANYHOW...I love your videos and as I work with RF/EMC its getting even more interesting since u began to work with all the cracks like Eric & Rick. Thanks!

[@kentswan3230]

@@SukramNotna The co-planar wave guides I implemented were all are on top sig (L1) and are impedance referenced to GND (L2). If I'm not woofing in the wind, pwr (L5) above the Bottom Sig (L6) provides shielding for the inner sig layers (L3, L4). For decoupling caps and power distribution, I'm now thinking that going to a 8 layer stack Sig1, Gnd, Pwr, Sig2, Sig3, Pwr, Gnd, Sig4 is one better option. Alternatively to provide isolation of S2 from Sig3 we could use a modified 8 Layer stackup of Sig1, Gnd, Sig2, Pwr, Pwr, Sig3, Gnd Sig4. In this way the decoupling short couples to the nearest gnd with the advantages that Robert has simulated.

[@tusisima]

I guess the reason you dont see different results for the via placement is that the simulation do not uses the physical size and dimension of the capacitors in its calculation. The distance (inductance) from internal plates in the capacitor to the via is smaller if you place the via's closer to the center of the capacitor.

[@franksu2100]

the capacitor of between the power and ground in 6 layer dominates the impedence. while 4 layer capacitor is not bigger enough to control the impedance. I guesse.

[@mikemarachov3230]

Robert, where did you learn Sipro?

[@RobertFeranec]

I am very lucky, that I can ask Keyisight directly if I am not sure about something. But I learned a lot just playing around.

[@tienphan1921]

Dear Sir, Can you turn on your auto subtitles in video. It may be helpful for a lot of people who not good at English. Thanks a lots

[@rfengr00]

Unfortunately all the cheap 4 layer processes have a thick core for layers 2 & 3, with foil/prepreg for layers 1 & 4. The outer layer impedance is too low and the inner too high. It ought to be two cores with a thin prepreg, adding the capacitance between 2 & 3, though I’m sure that costs more. I do all my PCB (RF laminates) the latter.

[@rjordans]

If you want to stick with the cheap options, maybe a thinner overall PCB can help you. Often you can get a 0.8mm or 1mm thick version of the PCB made which will have the space between layers 2 and 3 greatly reduced. For big boards there will be quite some mechanical impact of this but these cheap options are mostly used for smaller boards anyway.

[@XiaZ]

It's upside down.

[@julioflorentino3321]

Interesting