How to improve your PCB Layout - Checking Nets

How do you check nets in your PCB? What is your special technique?
Links:
High Speed PCB Design Rules (Lesson 4 of Advanced PCB Layout Course): • High Speed PCB Design ...
See how signals are travelling in your PCB: • See how signals are tr...
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[@АннаЗелезинская-х3н]

I am just entering the field of PCB development. And I wanted to express my gratitude to you for such informative and useful videos! Thank You!

[@vasilisvasilopoulos5276]

31:15 The reaction was spot on ! Thanks for the videos Robert!

[@guillep2k]

Master class!! Thank you, Robert! I don't have enough experience to give any opinions about the questions you asked, but I like that you do because other people come here and share their knowledge. I'm really happy about the kinds of videos you've been posting. Keep up the good work!

[@RobertFeranec]

Thank you very much guillep2k

[@dvatp]

Only comment I'll make about routing "every other signal" at 50 ohms is that the width of the traces will not necessarily be the same on different layers, as impedance is influenced by the stackup height (the vertical gap between the signal layer and its reference plane). Best to simply create a "width" rule for each layer to comply with 50 ohms SE impedance and make sure all traces on those layers conform to the rules via DRC. Naturally, it's important to do this before routing or you'll be pulling up a lot of traces (or manually resizing them). Another great video, Robert. Keep 'em coming!

[@RobertFeranec]

Thank you dvatp. Very good point. I should mention that. PS: I route my PCBs differently - I use the same width (usually 0.1mm for high density PCBs) and when PCB is finished I adjust the track width and change it to a number between 0.075 to 0.1mm to meet 50 OHM impedance based on PCB manufacturer recommendation.

[@kazz7148]

Thanks!

[@RobertFeranec]

Thank you very much

[@lucasdias2006]

Robert, Great video, congratulations. I once attended a lecture by Rick Hartley called "What your Differential Pairs Wish You Knew" where he presents a study of mismatch net length on purpose of differential pairs, and the most important thing to me that he said is that for a signal of 5GHz, it could present a mismatch net length of 1.5 mm (which is a lot to me). Maybe because of studies like these, that reference designs do not worry about match net length. Thank you.

[@RobertFeranec]

Lucas, very interesting. I have seen the video around, I will watch it. Thank you for the tip!

[@SaieenTwist]

Great video Sir. May you make a video of layout considering the EMC compliance?

[@RobertFeranec]

Thank you Masood. PS: I am thinking to have a recorded call with EMC expert. Do you have any specific questions?

[@SaieenTwist]

@@RobertFeranec I have a couple of questions for PCB considering the EMC compliance 1) Should ground and powers be coupled to Shell(BODY) of enclosure or DC-DC converter? If yes, how should they be coupled, resistvely or capacitively? Or should grounds be directly coupled? 2)How should PCB layer stackup be arranged? 3)Do we need ground planes if we have only power distribution on a board and no high frequency signals??? 4) How to reduce conducted noise of DCDC. It is noticed that after a certain level noise does not reduce even if you increase the value of output coupling capacitor. 5) While making a mixed design(having multiple grounds) PCB, does all grounds be coupled capacitively with each other? Should we use localised ground poygons on a power distribution board where dcdc converters or controllers(acquisition circuit) are placed? Does these polygons can be kept isolated from other grounds?

[@tarkbayraktar9000]

Hi, Robert. I think u should make a video on phase matching u mention at 27:50 by using signal integrity feature of Altium. It would be very helpfull to simulate on different situations.

[@inhcongnguyen4110]

Great video.! Wish you great health for even more useful videos for the e-community!

[@RobertFeranec]

Thank you Dinh. Take care.

[@andredevilliers0]

Hi Robert, thank you very much for the interesting video. I always feel the more I know, the less I know. Eventually it becomes so difficult to make decisions and I question everything I do.

[@tchiwam]

I like to have the edge travelling as soon as possible on the same front too. I also like to keep each side of the pair with as much inner and outer path on length path differential pairs.

[@yogirajkhandagale9494]

Very informative. Thanks Robert

[@RobertFeranec]

Thank you very much Yogiraj

[@DiegoColl44]

Video is extremely helpful... thanks Robert..!!

[@RobertFeranec]

Thank you very much Diego

[@gudimetlakowshik3617]

Another master piece from the master....thanks a lot...!!

[@RobertFeranec]

Thank you very much Gudimetla

[@romank438]

Hi Robert, nice and useful videos. Regarding the via topic at 15:35 I'd slightly disagree. Nailing a via directly at the 0R resistor(s) would make the caps slightly less effective. The existing layout is not too bad after all in that spot. Keyword "eye of the needle" routing: coming from the 0R to the pad of the cap, leaving the pad, going to the next cap's pad and then to the via. So the caps are as much inline as they can be, no stubs. Your proposal means, the caps need another via to be connected, what adds impedance. It might not make a difference in this PCB, is more a general approach for routing supply lines. BR Roman

[@sharana.p5921]

Omg thank you Mr. Robert Feranec. I have a request. Please make a video of impedance controlled routing and where to find the impedance value of particular signal. Please consider to do it. Thank you.

[@RobertFeranec]

For this I use information from PCB manufacturer - based on your stackup they will tell you what track parameters you need to use for specific impedance.

[@sharana.p5921]

@@RobertFeranec where to find the required impedence from datasheet. Thank you for the reply

[@RobertFeranec]

@@sharana.p5921 It is often in CPU design guideline. But there are some generic guidelines what you can find on the internet e.g. as I mentioned in the video you can try to search for "com express design guide"

[@sharana.p5921]

@@RobertFeranec thank you so much ❤️

[@alexshei5061]

Thank you for the video. How do you usually choose the hole size of the via? What factors does it depend on?

[@ismailovali6368]

Thank you so much Robert, I like you very much :)

[@delereorbem]

Hi Robert, Thanks for this video it was very useful. I was looking for the best way to define layers doing footprint or routing board and in these layers, what I must considerate to generate pick and place files? I had always this questions and I was looking in your videos but I can't find it.

[@siddharthmali5841]

Great video sir.

[@RobertFeranec]

Thank you Siddharth

[@TheTrueCBaer]

About the phase matching issue, it is even possible that the pins are not phase matched. Thats why Touchstone- and IBIS-files exist. If you know how to deal with them please show us. 46:49 "But you could use the length between the pads", I had a PCB fail because of this. It was a RF switch and not a resistor and the electrical length was much longer than the pad spacing. Board was for up to 2.4 GHz. btw. "The more I learn about it the more I'm confused" its because it is High Frequency design, you are welcome.

[@RobertFeranec]

Thank you cBaer. PS: Interesting to hear, that PCB fail.

[@TheTrueCBaer]

​@@RobertFeranec It was a circuit for phased array antenna. The circuit is part of estimating the azimuth and elevation of a transmitter. The task of the PCB is to take 4 RF inputs, phase shift them, and add then to a single output (over simplified). The phase shifts are switchable. In the circuit are two RF-paths in parallel which must have the same electrical length. One path has tree RF-switches, the other don't. I designed the PHYSICAL length to be equal on both paths. That was a mistake because the ELECTRICAL length of the RF-switches is longer than the physical (micro strip equivalent). This additional electrical length added to much additional phase shift and the signal was beyond usable (at around 2.3GHz). The circuit was from before my time with the company, and i have to redo it because of discontinued parts and a few other issues. I used QUCS to simulate the RF in my design. It can handle Touchstone files. To Measure my PCB i used the NanoVNA V2 together with GNU Octave.

[@jimjjewett]

Why are the paths taking so many extra twists? For example, at 25:00, in the reference design, there appears to be two sets of differential pairs running up the center. But the right pair jogs backs and forth several times, and the left pair goes up, comes back down, and circles around a pair of components. Is this because of length-matching with something that isn't visible?

[@RobertFeranec]

Yes, these are clocks for separate DDR4 banks - length matching is needed for them.

[@Filip3146]

At 5:40 we are looking at a capacitor connected on the 3.3V bus of some power supply and Robert, rightfully so, says that we are looking for a low impedance. Using MLCCs is critical because when minimizing impedance, what we are really interested in is minimizing loop inductance beyond the self-resonant frequency point for a given capacitor value/size. In this case, I would submit that the layout is bad due to two things primarily. The first one is that you are going out of the capacitor pad with long traces at least for one side, thus the loop inductance is increased. But let's say you can't move them closer due to space constraints on other layers. The second one is the decision to use two traces that are close to each other to connect to the vias that then connect together on some power plane. This creates two individual inductors that run side by side between the pad of the capacitor and the 3v3 plane. Bad enough they also run through the vias that add up 1-2nH depending on their structure. The two inductors are now coupled and their equivalent inductance increases since the current flow in both of them is in the same direction. The design IS worse than the alternative polygon given the same placement. I am NOT saying that the capacitor won't work in this case, it will probably be fine. But the two routing alternatives are, in my young lad opinion, not equivalent in performance. At 25:00 on the reference design phase matching, I would wager they did their skew budget and got the two edges inside their linear region without any additional matching. That is, for a roughly estimated 50ps rise time in that 20%-80% region they have enough skew length in the order of millimeters before things break, so they did no bother. Again, not an SI professional so if this is wrong or I made wrong assumptions please let me know.

[@RobertFeranec]

Very nice feedback Filip. Thank you!

[@Filip3146]

@@RobertFeranec No, I have to thank you for investing the time and resources in creating all the videos on this channel. I've learned so much from you and the guests you brought, especially in your latest videos concerning SI/PI. I don't think I am wrong in saying that the entire community appreciates and values all the videos you make and we are eager to see the next one. Thank you and keep up the good work.

[@lukamarin9622]

I would had liked to actually see you doing those improvements you talk about. Much more to learn, in that case.

[@fabiopolvo039]

Robert, At least 3 vias for that power net. I 'm very conservative about fails and longitivity of the circuit. My law is the more important is the net, more mitigation we apply.

[@hjups]

Very insightful! I agree with all of the points you made, though never conisdered decoupling the vias to power plane changes (like you mentioned early on). For the DSI to LVDS chip, are you sure that it's connected correctly? I have been looking at using the same chip on one of my boards and as I understand it, the channels are matched and cannot be split (though perhaps I missed something). I.e. DSI channel A goes to LVDS channel A, and DSI channel B goes to LVDS channel B. So by connecting both LVDS channel A and B, but only DSI channel A, the LVDS channel B signals will never have data on them. Or did you explicitly test / find a way to break the one DSI channel into 2x LVDS channels? Package length matching has always confused me. When is it important to include the internal package lengths in your length matching? Or do the routing guidelines already account for those length mismatches? (sort of like how PCIe has limits for the botherboard and for the PCIe cards, which combined are the total tolerance for the signal). For the LPDDR4 data group, is it worth adding the intermediate layer to move the vias to a better position like the board did? Or would you be better off only using one via per chip to change layers? For the PCIE REFCLK signal, phase matching may still matter even at 100 MHz. My understanding is that the point of the signal is to provide a very clean reference clock to synchronize the two ends (root and endpoint). So if you have a phase mismatch, that could potentially add jitter to the clock edge. So even though it's low frequency, it's the edges that really matter (that's why you need to use special oscillators to generate that clock) For unnamed nets, you could always take the opposite approach. If it's unnamed, then it should be routed as short as possible (since unnamed nets are usually between reference signals / RC filters, etc.).

[@RobertFeranec]

Thank you hjups. Very nice feedback. PS: LVDS - As I know, they are still testing the chip. Datasheet says "Supports single channel DSI to dual-link LVDS operating mode" - that could be what you mean? They use the chip with 1 DSI. Also there is plan B - the chip is placed and routed the way that it can be easily replaced e.g if they decide to use different chip or if someone needs a different interface. Package length: I include it when the chip manufacturer shares the information .. otherwise I assume, they did lengthmatching inside of the chip. DDR4: 1 via would also not be perfect - a very long stub ... and uVIA saves space ... so uVIA won. But would be interesting to simulate it (I asked some people, but have not got any answer back yet). PCIE REFCLK: That is a very interesting point. Thanks!

[@hienbk2404]

Hi Robert, Could you explain why the resistor symbol of schematic has the polarity mark?

[@RobertFeranec]

It is pin 1 mark and it is useful when you need to replace components (sometimes that happen) - so when replacing them, you know in schematic how to rotate the new symbol, so it will be compatible with rotation of your footprints which may already be placed in your PCB.

[@hienbk2404]

@@RobertFeranec thank you for sharing

[@Antyelektronika]

Hi Robert, this video is really good, more and more videos about layout. But could you make some videos about size of via-s, what kind of size we should use where and also about width of traces and also about net classes. It is only my ideas and your know how will be helpful. thank you :)

[@RobertFeranec]

Thank you Patryk. PS: There is nothing really special about VIAs. I often only use 1 or two kind of VIAs in PCB - usually the smallest cheapest via (eg 0.45mm/0.2mm), possibly smallest uVIAs (0.27/0.1mm). If I need it for higher currents, I just place number of them. Track width for signals is usually based on required impedance e.g. 50Ohms for specific PCB stackup. This may help: kzbin.info/www/bejne/hKq5m5psYtyZrLs

[@RoniVolkers]

Robert, your videos are excellent, thanks for sharing your knowledge. Just one question, I noticed that some polygons have 90º edges. Is there any configuration that avoids this characteristic? In Eagle, for example, even if the pad has 90º edges, the shape of the polygon around that pad takes the form of 45º curves.

[@RobertFeranec]

Thank you Ronimar PS: I have not seen anything automatic in Altium for this.

[@parkuorman]

Hi Robert and thanks for great videos, I've learned a lot by looking your ways of doing the layout. I as well have one question or subject to discuss. My work environment is production test. Many times there are discussions with customers about test points and ways how to test the boards. There are many different perspectives of ICT and functional testing need and coverage. Sometimes it is a question of circuit sensitivity while adding potential test option. May you share your opinion on high volume production testing? Layout considerations for test? Or even design for manufacturing guides. Thanks!

[@RobertFeranec]

Thank you Karolis. This topic is on my list - just need to find someone who has experience with very high mass production testing and can share the information. I am also very curious to know how big companies do it.

[@PG-pe5oc]

Hello sir thank you for your help. I have One question that how to decide width or area of copper pour in PCB for particular current. For example 1A current

[@MuhammadAhsan-rr4js]

Hello Sir. First time I saw you, you are dispointeed from, why we study so much about signal integrity related to hardware designing, if someone board is working without extra effort but believe me sir once is goes to production and installed in actually scenario it will create lot's of problem which no nobody understands this only you who knows the basic reason, so keep it up. Thanks for sharing and teach as which make us better hardware design engineer. Thanks alot . Respected

[@RobertFeranec]

Yeah - it is sometimes confusing. It is so exciting to learn new stuff and then you take a reference design and .... a lot of stuff is just ignored. I should find a very high speed open source design and have a look at how they do it ..... that could be interesting. If anyone knows such project, please let me know.

[@MuhammadAhsan-rr4js]

@@RobertFeranec yeah sure sir. But I remember you server board design view which is enough for reference this stuff

[@RobertFeranec]

@@MuhammadAhsan-rr4js The server design is very nice ... too nice :) The chip pinout is designed perfectly, a lot of space ... they knew what they were doing. Yes, there is a lot to see. Still it would be nice to see a design where they have to compromise ... limited space, bad chip pinout design etc. Maybe I will find something.

[@giannisasp1208]

@@RobertFeranec Yes that would be very nice to watch Robert! :) I would have the same questions as you... Did they compromise because they knew what they where doing or by mistake? You can't tell most of the times unfortunately... Maybe knowing when you can compromise, how much, and how to do it, is one of the hardest things to do...

[@sharana.p5921]

I have a doubt. In altium Interactive Length Tuning , there's a option called step for each parameters. I still confused what is that?

[@jessicav2031]

Imagine trying to diagnose the problem with a differential data line which is "just on the edge" of not working. It could be a nightmare!

[@RobertFeranec]

I agree .... PS: I just made a note to maybe make a video with some simulations vs phase matching.

[@beamray]

hey. IMHO, 2nd one with double tracks can cause problems in manufacturing, unbalanced copper for big VDD_3V3 capacitor would cause problems in assembly. About diff. clocks Ref board has short connection for that kind of edge, also phases are matched in the end. But it is not good enough. Such things should be simulated. I had a board with DDR3 and FPGA with no length or phase matching at all, but tracks was too short to do it anyway.

[@theondono]

I’d do that 3.3V_VDD V shaped connection with a polygon too. That split is significantly worse when you consider that resistance on a pcb is by square. That kind of shape is reminds me of the cuts used in laser trimmed resistors to increase value, which is not what you’d like for a supply line.

[@RobertFeranec]

I agree

[@paulpaulzadeh6172]

many of your trace are not connected at center of pad , they come inside pad with angle ( it is bad ) , during manufacture you may get etching problem , you also have a lot of penetration by vias, copper should go between copper shape area , a lot of inductance is made but this via , tear drop should be used too to improve etching process , recommend you see your layout under microscope when you get it from manufacture , then you will see

[@theondono]

That has been an issue for a long time in PCB manufacturing, but for modern pcb manufacturing this is not really a big issue anymore. I’ve really haven’t seen acid trap problems for years now, even in mid-range manufacturers.

[@RobertFeranec]

Thank you very much Paul. PS: I would like to clarify, this is not my design. Still, as Xavi mentioned, many things will not be a problem - at least when a good PCB manufacturer is used. Some time ago I asked many questions of a PCB manufacturer, it is in one of my videos ... here: kzbin.info/www/bejne/nGfCpKmIg6-MotU He also talks about tear drop - if PCB manufacturer considers it would be a risk for them do not have them, they will add them automatically.

[@paulpaulzadeh6172]

@@RobertFeranec well , I design for Class 3 IPC -A-610 , high level for DFM ( Design for Manufacture ) Space , medical, military's application , some time PCB should handle a lot of G force in some case , but anyway if you want sell it in ebay that not be a problem ,

[@roderickdiaz3834]

please enable subtitles to your videos

[@RobertFeranec]

Hmm, they are always enabled, they are just not always created. I am not sure why.

[@movax20h]

At 1600MHz, we will have 3200M edge changes per second. Assuming worst case of 300e6 m/s, that translates to edges spaced 94mm apart. That is huge. So I think phase matching is nice to have, but not a big deal until you are at 10GHz, where edges will be about 15mm apart. And phase matching to about +/-5% would mean you need phase matching length to be about 1.5mm accurate. Especially if you don't have any other high speed signals nearby to copoul / crosstalk, I don't think there is much to worry about. I am not RF or high speed signal engineer, but it sounds logical to me.

[@RobertFeranec]

Thank you movax20h for your feedback

[@Usturam]

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