RTL Design - APB Protocol | QuickSilicon | Hardware Design

  Рет қаралды 37,542

QuickSilicon

QuickSilicon

Күн бұрын

Пікірлер: 46
@QuickSilicon
@QuickSilicon Жыл бұрын
Checkout the our recently launched RTL Design course: quicksilicon.in/ The course covers bunch of more interesting problems and high quality explanation videos consisting of microarchitecture design and line-by-line RTL walkthrough.
@jayalakshmikolla9516
@jayalakshmikolla9516 3 жыл бұрын
Sir the lecture is good ..please post more videos on AHB,AXI protocol design & verification using uvm in future ...Thanks a lot sir.
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@Mr.karnatakahacker
@Mr.karnatakahacker 3 жыл бұрын
Initially I didn't understand at last got the idea..awesome lecture video..plz come up with more classes
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@ganauvm270
@ganauvm270 3 жыл бұрын
really amazing. can you please make the video for AHB RTL design?
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@prashant.yt.99
@prashant.yt.99 3 жыл бұрын
video is awsome.. small suggestion kindly have micro architecture diagram before starting with RTL
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Prashant, Noted. :)
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@venkateshiyer5073
@venkateshiyer5073 2 жыл бұрын
very good session, pls provide further protocols in a similar fashion
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Hey Venkatesh, we are working on releasing an RTL Design course which would have videos like these. We should be launching it soon.
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@richmondmagallon6948
@richmondmagallon6948 Жыл бұрын
thanks for the video! I have a question, how exactly will the system know if it will go to idle? aside from PREADY, what port is monitored for it to go to idle?
@tomurkin5563
@tomurkin5563 Жыл бұрын
Is this video discussing AMBA 3 APB?
@adarshwarkhade5480
@adarshwarkhade5480 3 жыл бұрын
come up with more videos.......... lecture was awesome....!!!
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Thank you Adarsh. We are working a RTL Design course and would soon be launching it.
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@minqingliang
@minqingliang 2 жыл бұрын
Hi Sir, thanks for the amazing tutorial video, I have a question regarding APB-JTAG model, after we request for read transaction in APB, how to get the ack back in JTAG? How to know whether the transaction is finished or not?
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@kirubavignesh6535
@kirubavignesh6535 Жыл бұрын
Hi sir, this video was extremely good.. Can you please post mipi spmi protocol design sir?
@justiceleague7406
@justiceleague7406 Жыл бұрын
How to write BFM for APB protocol? Can anyone share a good source to get code details?
@pranathinalam2345
@pranathinalam2345 3 жыл бұрын
such an amazing lecture, Thanks
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@arunkumargunturu9351
@arunkumargunturu9351 2 жыл бұрын
Please post videos on spi protocol 3 wire and 4 wire using rtl
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@SepurBhavana-zz6tz
@SepurBhavana-zz6tz 8 ай бұрын
what is the difference between PWakeup and PEnable signal?
@elcademy4241
@elcademy4241 9 ай бұрын
There is a mistake here. The Addr signal should be stable at Psel but it is changing at Penable_o signal. Sir, could you please comment on it? @line 75 : instead of assign paddr_o = {32{apb_state_access}} & 32'hA000; it should be: assign P_addr= {32{APB_st_SETUP|APB_st_access}} & 32'hA000;
@QuickSilicon
@QuickSilicon 8 ай бұрын
Yes, that is indeed a bug and I didn't realise then. Thank you for pointing it out. I will fix the code on EDAPlayground soon.
@rizeenshaikh4056
@rizeenshaikh4056 2 жыл бұрын
We are writing one data in one address what should be done for writing in multiple addressess n burst data?
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Hey Rizeen, In order to do so you would need a protocol which supports burst transactions (like AXI). The protocol then allows you to write to multiple addresses using a burst mode.
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@lohith1237
@lohith1237 3 жыл бұрын
sir can you plze write full enviornment in system verilog like transaction,generator driver,etc
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Hey Lohith, you could follow this: www.linkedin.com/posts/raulbehl_100daysofrtl-rtldesign-verification-activity-6969146294950875136-kuHh?
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@SepurBhavana-zz6tz
@SepurBhavana-zz6tz 8 ай бұрын
Why aren't control signals being active from setup phase itself?
@QuickSilicon
@QuickSilicon 8 ай бұрын
Yep, those should have been valid in the setup phase itself. That's a bug which I did't realise then!
@sainadhreddy9606
@sainadhreddy9606 3 жыл бұрын
Can you please design AHB Protocol too .
@ashmitaprakash9535
@ashmitaprakash9535 3 жыл бұрын
Hi, did you find anything for AHB?
@javedalam7027
@javedalam7027 2 жыл бұрын
@@ashmitaprakash9535 yes
@bhadrappavadageri1818
@bhadrappavadageri1818 2 жыл бұрын
@@javedalam7027 can you share
@QuickSilicon
@QuickSilicon 2 жыл бұрын
Hey Sainadh, We are working on releasing a RTL Design course and would try to cover the AHB protocol as well.
@QuickSilicon
@QuickSilicon Жыл бұрын
We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?
@sahanargowda15
@sahanargowda15 Жыл бұрын
Can I get this code pls?
@QuickSilicon
@QuickSilicon Жыл бұрын
You can get it from here: quicksilicon.in/course/rtl-design/module/events-to-apb
How to Design a Network Messaging Protocol!
24:14
hoff._world
Рет қаралды 12 М.
Verilog, FPGA, Serial Com: Overview + Example
55:27
hhp3
Рет қаралды 10 М.
Human vs Jet Engine
00:19
MrBeast
Рет қаралды 164 МЛН
Friends make memories together part 2  | Trà Đặng #short #bestfriend #bff #tiktok
00:18
UFC 308 : Уиттакер VS Чимаев
01:54
Setanta Sports UFC
Рет қаралды 831 М.
APB Protocol Read Write Transactions | with & without wait states | AMBA #APB PART1
19:14
Just enough assembly to blow your mind
29:31
Kay Lack
Рет қаралды 116 М.
Pcie (pci express) interview
54:51
RJ
Рет қаралды 6 М.
How do Graphics Cards Work?  Exploring GPU Architecture
28:30
Branch Education
Рет қаралды 1,1 МЛН
FASTEST Way To Learn Coding and ACTUALLY Get A Job
10:44
Brian Cache
Рет қаралды 1,1 МЛН
LeetCode solution in Golang - Gas Station
17:06
Mandu 2 Fundu
Рет қаралды 36
Systemverilog | Test Bench Environment | Half Adder
1:18:39
vlsi_training
Рет қаралды 40 М.
Human vs Jet Engine
00:19
MrBeast
Рет қаралды 164 МЛН