RTL Design - APB Protocol | QuickSilicon | Hardware Design

[@QuickSilicon]

Checkout the our recently launched RTL Design course: quicksilicon.in/ The course covers bunch of more interesting problems and high quality explanation videos consisting of microarchitecture design and line-by-line RTL walkthrough.

[@jayalakshmikolla9516]

Sir the lecture is good ..please post more videos on AHB,AXI protocol design & verification using uvm in future ...Thanks a lot sir.

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@Mr.karnatakahacker]

Initially I didn't understand at last got the idea..awesome lecture video..plz come up with more classes

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@ganauvm270]

really amazing. can you please make the video for AHB RTL design?

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@prashant.yt.99]

video is awsome.. small suggestion kindly have micro architecture diagram before starting with RTL

[@QuickSilicon]

Prashant, Noted. :)

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@venkateshiyer5073]

very good session, pls provide further protocols in a similar fashion

[@QuickSilicon]

Hey Venkatesh, we are working on releasing an RTL Design course which would have videos like these. We should be launching it soon.

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@richmondmagallon6948]

thanks for the video! I have a question, how exactly will the system know if it will go to idle? aside from PREADY, what port is monitored for it to go to idle?

[@tomurkin5563]

Is this video discussing AMBA 3 APB?

[@adarshwarkhade5480]

come up with more videos.......... lecture was awesome....!!!

[@QuickSilicon]

Thank you Adarsh. We are working a RTL Design course and would soon be launching it.

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@minqingliang]

Hi Sir, thanks for the amazing tutorial video, I have a question regarding APB-JTAG model, after we request for read transaction in APB, how to get the ack back in JTAG? How to know whether the transaction is finished or not?

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@kirubavignesh6535]

Hi sir, this video was extremely good.. Can you please post mipi spmi protocol design sir?

[@justiceleague7406]

How to write BFM for APB protocol? Can anyone share a good source to get code details?

[@pranathinalam2345]

such an amazing lecture, Thanks

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@arunkumargunturu9351]

Please post videos on spi protocol 3 wire and 4 wire using rtl

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@SepurBhavana-zz6tz]

what is the difference between PWakeup and PEnable signal?

[@elcademy4241]

There is a mistake here. The Addr signal should be stable at Psel but it is changing at Penable_o signal. Sir, could you please comment on it? @line 75 : instead of assign paddr_o = {32{apb_state_access}} & 32'hA000; it should be: assign P_addr= {32{APB_st_SETUP|APB_st_access}} & 32'hA000;

[@QuickSilicon]

Yes, that is indeed a bug and I didn't realise then. Thank you for pointing it out. I will fix the code on EDAPlayground soon.

[@rizeenshaikh4056]

We are writing one data in one address what should be done for writing in multiple addressess n burst data?

[@QuickSilicon]

Hey Rizeen, In order to do so you would need a protocol which supports burst transactions (like AXI). The protocol then allows you to write to multiple addresses using a burst mode.

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@lohith1237]

sir can you plze write full enviornment in system verilog like transaction,generator driver,etc

[@QuickSilicon]

Hey Lohith, you could follow this: www.linkedin.com/posts/raulbehl_100daysofrtl-rtldesign-verification-activity-6969146294950875136-kuHh?

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@SepurBhavana-zz6tz]

Why aren't control signals being active from setup phase itself?

[@QuickSilicon]

Yep, those should have been valid in the setup phase itself. That's a bug which I did't realise then!

[@sainadhreddy9606]

Can you please design AHB Protocol too .

[@ashmitaprakash9535]

Hi, did you find anything for AHB?

[@javedalam7027]

@@ashmitaprakash9535 yes

[@bhadrappavadageri1818]

@@javedalam7027 can you share

[@QuickSilicon]

Hey Sainadh, We are working on releasing a RTL Design course and would try to cover the AHB protocol as well.

[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@sahanargowda15]

Can I get this code pls?

[@QuickSilicon]

You can get it from here: quicksilicon.in/course/rtl-design/module/events-to-apb